Renesas M65881AFP manual Power sequences System power-on sequencing, Init Scdt Scshift Sclatch

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M65881AFP

13. Power sequences

System power-on sequencing

* Refer to following figure.

Power(Vddxxx, HPVddxxx,

XVdd, XOVdd, DVdd, BFVdd)

Power OFF Power ON

Master clock (XfsoIN,XfsiIN)

INIT

SCDT

SCSHIFT

SCLATCH

X

X

X

X

X

Over 5msec(*1)

Over 0sec(*2)

Over 2/fso(*3)

*1 After a power supply and Master clock become to stable, INIT pin must be "L" over 5msec.

*2 Data transfer is possible right after INIT release.

*3 Until SCLATCH is operated, a period over 2/fso ( fso=48kHz, over 42µsec ) is necessary after INIT release.

Rev.1.00 2003.05.08

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Contents Features Main SpecificationSystem Block Diagram DescriptionPIN Configuration OUTL1 Data OUTL2 Lrck OUTR2 HPOUTL1 HPOUTL2HPOUTR2 Absolute Maximum Ratings Parameter Level Input Voltage Input Leek CurrentCharacteristics Evaluation Circuit GNDPIN Description Explanation of Operation DATA,BCK,LRCKSCDT, SCSHIFT, Sclatch MCKSEL, XfsoIN, XfsoOUTScdt Scshift Sclatch ASYNCEN2=enable FsoI, SflagOUTL1, OUTL2, OUTR1, OUTR2 PWM output controlNSPMUTEL,NSPMUTER H ChselPower supply and GND HPOUTL1, HPOUTL2, HPOUTR1, HPOUTR2Init TEST1, TEST2Power sequences System power-on sequencing Init Scdt Scshift SclatchSerial Control NSLMT1,2Mantissa Data decimal value 128 Characteristics of Soft Mute function MODE1 MODE2IFMT0 IFMT1 IBIT0Rev.1.00 System2 Mode Rev.1.00 AC Characteristics AC Characteristics Timing ChartDSP MCU Application ExampleDiagram PackageM65881AFP