Renesas M65881AFP manual PIN Configuration

Page 2

M65881AFP

PIN CONFIGURATION

 

 

 

 

VddL

1

 

 

 

 

 

 

 

OUTL1

2

 

 

 

 

 

 

 

VssL

3

3.3V

 

 

 

 

OUTL2

4

system

 

 

 

 

 

 

 

 

XOVdd

5

 

 

 

 

 

 

 

XfsoOUT

6

 

 

 

 

 

 

 

XOVss

7

 

 

 

 

 

 

1.8V

DVdd

8

 

 

 

 

system

 

 

DVss

9

 

 

 

 

 

 

 

MCKSEL

10

 

 

 

 

 

 

 

SCDT

11

 

 

 

 

 

 

 

SCSHIFT

12

 

 

 

 

 

 

 

SCLATCH

13

 

 

 

 

 

 

3.3V

NSPMUTE

14

 

 

 

 

system

 

 

INIT

15

 

 

 

 

 

 

 

 

LRCK

16

 

 

 

 

 

 

 

BCK

17

 

 

 

 

 

 

 

DATA

18

 

 

 

 

 

 

 

BFVdd

19

 

 

 

 

 

 

 

BFVss

20

 

 

 

 

 

 

 

XfsiIN

21

 

 

 

 

 

 

Rev.1.00 2003.05.08

page 2 of 23

PWM output

for Power Stage

PWM output for Headphone

42

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26

25

24

23

22

VddR

OUTR1

VssR

OUTR2

VssLR

XVdd

XfsoIN

XVss

HPVddL

HPOUTL1

HPVssL

HPOUTL2

HPVddR

HPOUTR1

HPVssR

HPOUTR2

TEST1

TEST2

SFLAG

FsoI

FsoCKO

3.3V system

Image 2
Contents System Block Diagram FeaturesMain Specification DescriptionPIN Configuration HPOUTR2 OUTL1 Data OUTL2Lrck OUTR2 HPOUTL1 HPOUTL2 Absolute Maximum Ratings Parameter Level Input Voltage Input Leek CurrentCharacteristics Evaluation Circuit GNDPIN Description Explanation of Operation DATA,BCK,LRCKScdt Scshift Sclatch SCDT, SCSHIFT, SclatchMCKSEL, XfsoIN, XfsoOUT ASYNCEN2=enable FsoI, SflagNSPMUTEL,NSPMUTER H OUTL1, OUTL2, OUTR1, OUTR2PWM output control ChselInit Power supply and GNDHPOUTL1, HPOUTL2, HPOUTR1, HPOUTR2 TEST1, TEST2Power sequences System power-on sequencing Init Scdt Scshift SclatchSerial Control NSLMT1,2Mantissa Data decimal value 128 Characteristics of Soft Mute function IFMT0 MODE1MODE2 IFMT1 IBIT0Rev.1.00 System2 Mode Rev.1.00 AC Characteristics AC Characteristics Timing ChartDSP MCU Application ExampleDiagram PackageM65881AFP