BenQ PE8700 manuals
Computer Equipment > Projector
When we buy new device such as BenQ PE8700 we often through away most of the documentation but the warranty.
Very often issues with BenQ PE8700 begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Projector BenQ PE8700 is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Projector on our side using links below.
27 pages 3.54 Mb
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BenQ PE8700 Service Manual
97 pages 1.76 Mb
2 Contents 3 1. 71 Benq Corporation THERMAL CONNECTORKEYPAD CONNECTOR72 RED -- D_INA[23..16] GREEN -- D_INA[15..8] BLUE -- D_INA[7..0]Optical Points Screw Holes SPARE for DVI interface Note: The Sil 503 does not support a standard I2C protocol. See data sheet page 22. 73 Note: For compatability with Sil504 place bypass resistorsInput Port 74 Benq CorporationLED2 LED3 SOURCE 1 G2 S 3 D BSN20(open) (open) 75 modify this areaRIGHT EDGEBOTTOM EDGELEFT EDGE Place the resistors as close to the RM1 pins as possible. RED -- D_INA[23..16] GREEN -- D_INA[15..8] BLUE -- D_INA[7..0] RM1_GP0 , RM1_GP1 Input Only or Output Only From Pin AE9, Former R22 From Pin B12, Former R25(PIO21) (PIO18) (PIO20) (PIO5) (PIO19) (PIO20) (PIO2) (PIO12) (PIO10) (PIO13) (PIO1) (PIO4) (PIO6) (PIO17) (INT1) (PIO29) (PIO21) Note: Instead of KM616V1000B, IS61LV25616-12T (256K x 16 bit 4M) can be stuffed for debug. (256K x 16Bit FLASH) (128KBytes SRAM) 76 Link to test board.Note: All outputs are disabled after power-up until IOCS_WR_SET_N is activated by software. ** Generate Harward RESET Singnal ** AME8500AF27 77 SOT23 78 Benq Corporation PIN41, 42 is prohibited by mechanical design, THIS PIN ONLY FOR TESTMEM_A11 -- Higher Bank Select (BA1) MEM_BS -- Lower Bank Select (BA0) 79 Termination resistors values = (traces impedance) x 2Test parts and resistors are located at the end of bus chain.VDD - Input buffers and the core supply (MEM_A11= =D_INA2_OVFL) 80 LAMPEN CIRCUITINPUTS, LAMPEN, LAMPLIZ, CWINDEX (Connector for DLP FALSH DOWNLOAD) LAMOLITZ CIRCUIT CWINDEX CIRCUIT INPUT SIGNALS FROM MAIN BOARD (IIC From Main CPU) (IIC From Computer) 81 DDP1010 Flash, Micro, Clocks, DAD1000 ControlMicro, Clocks ,SR16 and Flash interface CLKIN U2B50MHz Clock (To SSI Motor) DDP1010 FLASH7229800219 AM29LV800BB-120EC Minimize Noise on PLL_VCCAMaster Clock (100MHz) Pixel Clock (74.25MHz) from Scalar (To MUSTANG) SERIES CONTROL PORT 1 SERIES CONTROL PORT 0 82 DDP1010 Video Input and DMD OutputVideo Inputs From Scalar RGB 888 Format (24bits) Video Syncs From Scalar LVDS Differential DataBus DDA LVDS Differential DataBus DDB (To Mustang DMD) (To Mustang DMD) LVDS Differential DCLKA LVDS Differential DCLKB LVDS Differential Series Control Bus A LVDS Differential Series Control Bus B U2C DDP1010 83 CDCR83 (DRCG) 3.3V Decoupling CapsRDRAM Memory Control LAMPEN Direct Rambus Clock Generator (DRCG) RDRAMRDRAM VDD (2.5V) DECOUPING CAPS 1.8V Rambus, JTAG and Customer Input VTERM (1.8V) Bulk Decoupling CapsRamBus Address Channel RamBus Data Channel A RamBus Data Channel B Termination Components U2A DDP1010 U9 CDCR83 K4R271669DU8 85 MUSTANG (HD2) DMDMUSTANG 86 DAD1000
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