BenQ PE8700 Iocsrdsetn CPUA3 CPUA4, IORD0N, IORD1N, KEYPAD0, INLTCH11, KEYPAD8, INLTCH21, Sbuffer

5 4 3 2 1

+3VS

D

		+3VS
		14	U7A
CPU_RD_N		1
	CPU_PCS0_N	2
		7	74VHC32

CPU_A3

CPU_A4

3IOCS_RD_SET_N

CPU_A3 CPU_A4

KEYPAD[0..9]

		+3VS
2	16		U14A		4
	A		Y0
1	G GNDVCC		Y3	7		IORD0_N
3	B		Y1	5
			Y2	6		IORD1_N
	8		74VHC139

KEYPAD0	RP20	47_RP	INLTCH1_1
	1	2
KEYPAD1	3	4	INLTCH1_2
KEYPAD2	5	6	INLTCH1_3
KEYPAD3	7	8	INLTCH1_4
KEYPAD4	1	2	INLTCH1_5
KEYPAD5	3	4	INLTCH1_6
KEYPAD6	5	6	INLTCH1_7
KEYPAD7	7	8	INLTCH1_8

		IORD0_N		RP21	47_RP
						+3VS
		KEYPAD8		RP22	47_RP	INLTCH2_1
			1		2
		KEYPAD9	3		4	INLTCH2_2
LAMP_PROTECT	1E1	WIRE_TP53	5	RP23	6	INLTCH2_3
			7		8	INLTCH2_4
TP53	1E1	WIRE_TP52	2		1	INLTCH2_5
TP52	1E1	WIRE_TP51	4		3	INLTCH2_6
TP51	1E1	WIRE_TP46	6		5	INLTCH2_7
TP46	1E1	WIRE_TP47	8		7	INLTCH2_8
TP47		IORD1_N		47_RP

	20
2	U13
	1A1	VCC
4
	1A2
6
	1A3
8
	1A4
11
	2A1
13
	2A2
15
	2A3
17
	2A4

11G

19 2G

74AHC244

	20
2	U15
	1A1	VCC
4
	1A2
6
	1A3
8
	1A4
11
	2A1
13
	2A2
15
	2A3
17
	2A4

11G

19 2G

1Y1	18	CP U_D0
	16	CP U_D1
1Y2	14	CP U_D2
1Y3	12	CP U_D3
1Y4	9	CP U_D4
2Y1	7	CP U_D5
2Y2	5	CP U_D6
2Y3	3	CP U_D7
2Y4
GND
10		CP U_D0
1Y1	18
	16	CP U_D1
1Y2
	14	CP U_D2
1Y3
	12	CP U_D3
1Y4	9	CP U_D4
2Y1
	7	CP U_D5
2Y2
	5	CP U_D6
2Y3
	3	CP U_D7
2Y4
GND

D

C

B

			+3VS
	CPU_WR_	N	14	U7D
			12
CPU_WR_N					11
	CPU_PCS0_N		13
CPU_PCS0_N
			7	74VHC32

				+3VS
+3VS					U8B
			14
IOCS_WR_SET_N		4			74HC132
					6
		5
	7

S_BUFFER

+3VS

	14
	9	8
RESET_N	10
	7	U8C
		74HC132

CPU_A1

CPU_A1CPU_A2 CPU_A2

IOCS_WR_SET_N

+3VS

R78

5.1K

OUT_BUFFER_OE_N

74AHC244

DVI_SCDT

SPAREI

CPU_D[0..7]

CPU_D[0..7]

+3VS

U17

20

RP24

47_RP

CP U_D0

OUTLTCH1_1

2

D1

VCC

Q1

19

1

2

CP U_D1

3

18

OUTLTCH1_2

3

4

D2

Q2

CP U_D2

4

D3

Q3

17

OUTLTCH1_3

5

6

CP U_D3

5

16

OUTLTCH1_4

7

8

D4

Q4

+3VS

CP U_D4

6

15

OUTLTCH1_5

1

2

D5

Q5

CP U_D5

7

14

OUTLTCH1_6

3

4

D6

Q6

16

CP U_D6

8

13

OUTLTCH1_7

5

6

D7

Q7

U14B

CP U_D7

9

12

OUTLTCH1_8

7

8

DLP_SPARE

14

12

D8

Q8

A

Y0

GND

15

G GNDVCC

Y3

9

IOWR0_N

IOWR0_N

11

RP25

47_RP

13

B

Y1

11

CLK

Y2

10

OUT_BUFFER_OE_N

1

OC

74VHC139

74ABT574

10

R75

R76

8

+3VS

10K

10K

CPU_D[0..7]

CPU_D[0..7]

U22

20

CP U_D0

2

D1

Q1

19

OUTSPARE1

CP U_D1

3

D2

VCC Q2

18

OUTSPARE2

CP U_D2

4

D3

Q3

17

OUTSPARE3

CP U_D3

5

16

OUTSPARE4

D4

Q4

CP U_D4

6

15

OUTSPARE5

D5

Q5

CP U_D5

7

14

OUTSPARE6

D6

Q6

CP U_D6

8

13

OUTSPARE7

D7

Q7

CP U_D7

9

12

OUTSPARE8

D8

Q8

IOWR0_N1

OUT_BUFFER_OE_N

11

CLK

GND

R106

R107

R108

R109

R110

1

OC

74ABT574

0

0

0

0

0

10

SPAREO

+3VS

R77

180

U18

2

VDD

3

RESETVCC

RESETVCC

GND

RES

1

AME8500BEET

R118

100K

2

R80

1K

3.3VRESET

3

D3

RESET_N

BAV99

1

C88

1U Z

10

MUX_SEL

TRIGGER SII141_PDO RM1_RST_N MCURESET POWERON WRITE_PROT DLP_SPARE

R111 R112 R113

0 0 0

Note:	All outputs are disabled
after	power-up until
IOCS_WR_SET_N is activated by		C
software.

B

		+3VS
C89	C90	C91	C92	C93	C94
0.1UF	0.1UF	0.1UF	0.1UF	0.1UF	0.1UF

A

** Generate Harward RESET Singnal **

VDD

3 SOT23

1	2
RST	GND

AME8500AF27

A

Benq Corporation

Project Code		Model Name			OEM/ODM Model Name
	99.J5877.001		HT720G				NA
Title		MAIN BOARD
Size	PCB P/N		PCB Rev.	Document Number				Rev.
<Size>	48.J5801.S02		S02	99.J5877.R22-C3-304-001				0
Date: Thursday, January 16, 2003				Sheet	8	o f	10
	Prepared By		Reviewed By			Approved By
	ANGEL HU	COLIN CHANG				BEN CHEN

5

4

3

2

1