Contents
Main
Contents
1.
2. Servicing Precautions
3. Engineering Specification
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Appendix A Optical Measurement
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Appendix B Design Verification Test Procedure
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Appendix D HD2 Front Projection Image Quality Specification
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Appendix E Supporting Timings
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Chapter 4 Spare Parts List
5. Black Diagram
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8. Alignment Procedure
-
- - -
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- -
364818
27
=
+
364818
=
+
12
(
- -
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Case x1>x0 & y1 > y0 :
Case x1<x0 & y1 < y0 :
Case x1>x0 & y1 < y0 :
Case x1<x0 & y1>y0
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9. Trouble Shooting Guide
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10. Factory OSD Operation
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5. Filter Bypass
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8.Pattern2 This page allows user to call up DLP DDP1010 series present patterns.
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11. Firmware Upgrade Procedure
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12. RS232 Codes
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Following is the list of Y-group:
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DLP Connector/POWER
CPU
Benq Corporation
THERMAL CONNECTOR
KEYPAD CONNECTOR
RED -- D_INA[23..16] GREEN -- D_INA[15..8] BLUE -- D_INA[7..0]
Optical Points
Screw Holes
SPARE for DVI interface
Note: The Sil 503 does not support a standard I2C protocol. See data sheet page 22.
Note: For compatability with Sil504 place bypass resistors
Input Port
Benq Corporation
LED2 LED3 SOURCE
1 G2
S
3 D
modify this area
RIGHT EDGEBOTTOM EDGELEFT EDGE
Place the resistors as close to the RM1 pins as possible.
RED -- D_INA[23..16] GREEN -- D_INA[15..8] BLUE -- D_INA[7..0]
RM1_GP0 , RM1_GP1 Input Only or Output Only
Link to test board.
Note: All outputs are disabled after power-up until IOCS_WR_SET_N is activated by software.
** Generate Harward RESET Singnal **
12
AME8500AF27
SOT23
Benq Corporation
PIN41, 42 is prohibited by mechanical design,
THIS PIN ONLY FOR TEST
MEM_A11 -- Higher Bank Select (BA1) MEM_BS -- Lower Bank Select (BA0)
Termination resistors values = (traces impedance) x 2
VDD - Output buffers
Test parts and resistors are located at the end of bus chain.
VDD - Input buffers and the core supply
(MEM_A11= =D_INA2_OVFL)
LAMPEN CIRCUIT
CWINDEX
(To DDP1010)
INPUTS, LAMPEN, LAMPLIZ, CWINDEX
(Connector for DLP FALSH DOWNLOAD)
DDP1010 Flash, Micro, Clocks, DAD1000 Control
Micro, Clocks ,SR16 and Flash interface
CLKIN
U2B
50MHz Clock
DDP1010 Video Input and DMD Output
Video Inputs From Scalar RGB 888 Format (24bits)
Video Syncs From Scalar
LVDS Differential DataBus DDA
LVDS Differential DataBus DDB (To Mustang DMD)
CDCR83 (DRCG) 3.3V Decoupling Caps
RDRAM Memory Control
LAMPEN
Direct Rambus Clock Generator (DRCG)
RDRAM
2.5V Regulator and Decoupling Caps DDP3P3V Decoupling Caps
Screw Holes
MUSTANG (HD2) DMD
U6A
MUSTANG
U6B
MUSTANG
DAD1000
DAD1000
--> (1U--> 0.22U) for more working margin
SSI COLOR WHEEL DRIVE CIRCUIT
Screw Holes
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For AD8183
This MUX is for seletion between BNC-RGB and DSUB_RGB
3_C
This MUX is for seletion between BNC_YPbPr and DSUB_BNC_RGB
2N3904 1_B 2_E
For AD8183
The voltage level of CB/CR is +0.35~-0.35 , add one diode to prevent uncertain 'ON' error
(open)(open)
This MUX is BUFFER of Composite and S-Video Open if -5V is not necessary
For AD8185 R=75
(open) (open) (open) (open)
I2C BUS SLAVE ADDRESS: 0x42 - W,0x43 - R
84.04431.037 1:TURN ON 0:TURN OFF
69.42001.021
2N3904 1_B 2_E
3_C
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