ADR0, Datack Hsout, Sogout Vsout, Adrin, Pb/G Ad Gin | BenQ PE8700

D

C

B

5

4

3

TP1	1
E1
TP3	1
E1
TP5	1
E1

TP7	1		(open)				(open)				(open)				(open)
E1
TP9	1
E1	1	4	3	2	1	4	3	2	1	4	3	2	1	4	3	2	1
TP11	1	CN1				CN2				CN3				CN4
E1		CN1				CN2				CN3				CN4
TP13	1	22P				22P				22P				22P
E1	1	5	6	7	8	5	6	7	8	5	6	7	8	5	6	7	8
TP15	1
E1

LP1 120 OHM

1	8D_INA8
2	7D_INA9
3	6D_INA10
4	5D_INA11
1	8	D_INA12
2	7	D_INA13
3	6	D_INA14
4	5	D_INA15

G0 G1 G2 G3 G4 G5 G6 G7

LP2 120 OHM

AD_R0

LP4 120 OHM

D_INA16

_ _ _ _ _ _ _ _

1

8

AD AD AD AD AD AD AD AD

AD_R1

2

7

D_INA17

AD_R2

3

6

D_INA18

AD_R3

4

5

D_INA19

AD_R4

1

8

D_INA20

AD_R5

2

7

D_INA21

AD_R63

6

D_INA22

AD_4R7

5

D_INA23

LP3 120 OHM

TP17

1

DATACK

E1

HSOUT

1R41

332

TP19

1

TP18

E1

SOGOUT

E1

VSOUT

1R42

332

1

C39

Y / R

AD_RIN

Y/R

47NF

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

64 63 62 61

3

G7

VDDVDDR0R1R2R3R4R5R6R7VDDGNDDATACKHSOUTSOGOUTVSOUTGNDVDGND VD

58

C40

REF_BYPASS+3VB_A2D

TP20

1

GND

60

0.1UF

2

GND

GND

59

E1

4

G6

REF BYPASS

57

SDA

G5

SDA

5

56

SCL

C41

G4

SCL

1

6

55

PB/G

AD_ GIN

G3

A0

PB/G

47NF

7

54

G2

RAIN

TP21

TP22

8

G1

GND

53

9

G0

U7

VD

52

E1

E1

10

GND

VD

51

+3VD

11

AD9883

50

VDD

GND

12

49

C42

B7

SOGIN

1

1

13

48

PR/B

AD _BIN

B6

GAIN

47NF

14

47

PR/B

B5

GND

15

46

B4

VD

16

45

B3

VD

17

44

B2

GND

HSYNC

18

43

B1

BAIN

19

42

B0

VD

20

GND VDD VDD GND GND VD VD GND COAST HSYNC VSYNC GND FILT PVD PVD GND MIDSCV CLAMP VD GND

41

GND

GND

(open)

R43

R44

R45

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

4

3

2

1

220

220

220

C43

0.1UF

CN6

For AD8185

22P

5

6

7

8

R=75

C44

MIDSCV

AD_SOGIN

AD_B0

LP6 120 OHM

D_INA0

1NF

+3VC_A2D

1

8

AD_B1

2

7

D_INA1

1

AD_B2

3

6

D_INA2

TP23

R46

AD_B3

4

5

D_INA3

D_INA4

1K

AD_B4

1

8

E1

AD_B5

2

7

D_INA5

AD_B6

3

6

D_INA6

2

AD_B7

4

5

D_INA7

1

LP5 120 OHM

VSYNC	1	2FLT	CN5	8	7	6	5	22P
1	1	2FLT	CN5	8	7	6	5	22P
	H _SYNC
R48	R47	C45		1	2	3	4
R48	R47	C45
51K	2.7K	82NK 16V

2	FILT	C46	(open)
		8200P K

1	TP2E12
E1 TP4
1	TP6
1	TP6
E1 TP8	E1
1	TP10
1	TP10
E1	E1

1TP12

1TP14

E1

1TP16

E1

D _HSYNC

D_VSYNC

AD_CLK

DVI_CLK

TP24

1

TP25

1 E1

TP26

1 E1

TP27

1 E1

TP28

1 E1

TP29

1 E1

TP30

1 E1

E1

1

D_INA[0..23]

D

AD_CLK

D_HSYNC

D_VSYNC

SDA

C

SCL

+5V_ADDVI

R116

0

R115

0

U22_ADCLK 1

U22

24

IN0A

VCC

2

23

DGND

OE

3

22

DVI_PDO

IN1A SEL A/B

L30 30 OHM

4

21

GND

VCC

OUTDINCLK

5

20

DIN_CLK

IN2A

OUT0

6

19

VCC

VEE

7

18

VEE

OUT1

C156

C155

8

17

9

IN2B

VCC

16

22P J

22P J

GND

OUT2

10

15

<Spec>

<Spec>

IN1B

VEE

11

14

GND

DVCC

R117

0

U22_DVICLK 12

13

IN0B

VCC

AD8183

+5V_AD

R118

0

C178

0.1U Z

-5V_ADDVI

B

-5V_ADDVI

+5V_AD

C188

1

U23

8

NC

V+

U23_CAP

2

1

2

7

+

CAP+

OSC

3

6

U23_CAP-

GND

LV

4

5

CAP-

VOUT

10U

2

16V

ICL7660S 5V

C187

+

C189

0.1U Z

10U

1

16V

-5V_ADDVI

+5V_ADDVI

A

U8

+3VD

+5V_AD

LD1117/SOT

+3VD

3

VIN

VOUT

2

C47

C48

C49

C50

C51

C52

C53

GND

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

4.7UF/16

1

+5V_AD

U9

3

LD1117/SOT

2

+3VC_A2D

+5V_AD

VIN

GND

VOUT

1

C65

+C66

C67

C68

4.7U/16V

1

10UF/16

0.1UF

0.1UF

2

2 1

+

C54

10UF/16

C55

0.1UF

C56

C57

C58

C59

C60

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

C61

0.1UF

C62

0.1UF

+3VB_A2D

C63 C64

0.1UF 0.1UF

C179

C180

C181

C182

C183

C184

C185

C186

0.1U Z

0.1U Z

0.1U Z

0.1U Z

0.1U Z

0.1U Z

0.1U Z

0.1U Z

A

Benq Corporation

Project Code

Model Name

OEM/ODM Model Name

99.J5877.001

HT720G

NA

Title

CONNECTOR BOARD

Size

PCB P/N

PCB Rev.

Document Number

Rev.

<Size>

48.J5810.S02

S02

99.J5877.R22-C3-304-004

0

Date:

Monday, February 17, 2003

Sheet

4

o f

8

Prepared By

Reviewed By

Approved By

ANGEL HU

ALEX HY TSENG

BEN CHEN

5

4

3

2

1

Image 93

BenQ PE8700 ADR0, Datack Hsout, Sogout Vsout, Adrin, REFBYPASS+3VBA2D, Pb/G Ad Gin, Pr/B Ad Bin, Midscv Adsogin ADB0, Sync

Contents

DLP Projector Contents Servicing Precautions Safety Precautions Minimum Engineering SpecificationPage Hdtv IEC Vcci Content Appendix a Optical MeasurementGeneral requirements A1. Brightness Practical consideration A2. Brightness Uniformity A5. Peak Contrast A9. Zoom Ratio Appendix B Design Verification Test Procedure PurposeTest Summary Test Order Definition Appendix C Drawings and Attachments Page Appendix D HD2 Front Projection Image Quality Specification Gray 10 test screen Gray 6 test screenWhite test screen Black test screen Red Ramp test screen Test Conditions as tested in OEM projector· Refer to for acceptance criteria, in specified order Image Quality Specification Appendix E Supporting Timings Support Timings by DVI-I Input Analog or Digital PC signalsPage Projector PE8700 99.J5877.B21 Spare Parts List BNC Black Diagram Packaging Description Appearance Description Page Procedure Alignment ProcedureOSD Default value used for color delay alignment Equipment Select Save Setting at Factory OSDFactory OSD Default value used for DVI-Analog color alignment Procedure Black Level Adjustment DLP brightness White Level Adjustment AD contrast---R,G,B gainOffset adjustment at low brightness AD R, G, B offset User setupwhite C15400k C26500k C37500k OSD Default value used for Ypbpr color alignmentYPbPr Component Equipment Gray Level AD Ypbpr Contrast, Brightness Procedure Pbpr Offset adjustment AD PB, PR Offset Saturation Level Scalar Case x1x0 & y1 y0 Factory SD User setupwhite C15700k C26500k C39300k Saturation Level Gray Level for Ycbcr Component Procedure Procedure Gray Level OSD Default value Value USERPictureGray Level for Composite Video & S-Video Equipment Additional Patterns used for color final check System trouble shooting Trouble Shooting Guide YES Main board trouble shooting SIL504 trouble shooting U4, U2 CPU U10 trouble shooting guide YES DMD board trouble shooting guide OK? Connector board trouble shooting guide Power board trouble shooting guide 鐐衒蘠耟  鞤矏矏耟礼袨蘠醥袓藜耟  韗齇耟  斉鞥觖罿蘠韘篧蚴礼  誜袨鷘矏篧袨ゾ篧礼榢譗む鞥觖蛂豽袕む醥藜罿袨矏篧ソ譂 Factory Factory OSD Operation STD Adj HD Adj Color Balance Filter Bypass Pattern1 DLP Pattern3 Pattern2 Test Mode Firmware Upgrade Procedure Page 12. RS232 Codes Page X00 Must be Reversed , no function X57 Picture by picture display Page Following is the list of Y-group Page ACK = Y1Y Page Page Page Mcureset Dvdoreset DeintdoneOpenable Mcureset Trigger Benq Corporation DIIN9 DIIN6 DIIN8DIIN7 DIIN4 Interlacedetect ResetdvdoCLK54 22DETECT 32DETECT Benq Corporation RM1CLKIN WIRETP31 RM1OP EnableMEMDQ14 WIRETP30 CP UD0 CP UD1 Resetvcc Powerontest Resetn SDA SCLResetvcc CPUA8 CP UD0 CPUS2 Resetn CPUA3 Cpurdn WIRETP52 INLTCH25 WIRETP53WIRETP51 INLTCH26 WIRETP46 INLTCH27 This PIN only for Test MEMDQ15 MEMDQ48 MEMDQ31 MEMDQ0MEMDQ30 MEMDQ1 MEMDQ14 MEMDQ49 Cwindex Circuit FLADDR16 FLADDR12 U2C CTMN1M CTM1M P2P5VIN Screw Holes Scrlr DDAN10 DDAN11 DDAN12 DDAN13 DDAN14 DDAN15 DAD1000 SSI Color Wheel Drive Circuit Benq Corporation 500 OHM Vsync Capp 1CAPP+CAP HSB Bnchs Voltage level of CB/CR is Datack Hsout ADR0Sogout Vsout Adrin Scin ResetCR1IN CB 1IN Sogy Sogyin Sogrca Racin Inta 1TURN on Larry Lin1 Resetzdvi RES Oclk INV Hsdjtr R101 ResetzdviRESETR111 Dviscl DVISCL3V Dvisda DVISDA3V