Cypress CY7C0851AV manuals
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Cypress CY7C0851AV Manual
32 pages 971.59 Kb
FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM CY7C0850AV, CY7C0851AVFeatures Functional Description 2 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV3 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV5 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AVFigure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View) Pin Configurations CY7C0850AV CY7C0851AV CY7C0852AV 6 Pin Definitions7 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AVMaster Reset Mailbox Interrupts 8 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AVAddress Counter and Mask Register OperationsCounter Reset Operation Counter Load Operation Counter Readback Operation Counter Increment Operation Counter Hold Operation 9 Counter InterruptRetransmit Mask Reset Operation Mask Load Operation Mask Readback Operation Counting by Two 12 IEEE 1149.1 Serial Boundary Scan (JTAG) 13 Maximum Ratings Operating Range Electrical Characteristics Capacitance 15 Switching Characteristics 16 JTAG Timing 17 Switching Waveforms Figure 8. Master Reset Figure 9. Read Cycle 18 Figure 10. Bank Select ReadFigure 11. Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31] 19 Figure 12. Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31]Figure 13. Read with Address Counter Advance 20 Figure 14. Write with Address Counter AdvanceFigure 15. Disabled-to-Read-to-Read-to-Read-to-Write 21 Figure 16. Disabled-to-Write-to-Read-to-Write-to-ReadFigure 17. Disabled-to-Read-to-Disabled-to-Write 22 Figure 18. Read-to-Readback-to-Read-to-Read (R/W = HIGH)23 Figure 19. Counter Reset24 Figure 20. Readback State of Address Counter or Mask RegisterA A n+3 A 25 Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read[39, 40, 41]26 Figure 22. Counter Interrupt and Retransmit[34, 42, 43, 44, 45]27 Figure 23. MailBox Interrupt TimingH X L H X High-Z Outputs Disabled LLHHD 28 Ordering Information256K 32K 64K 128K 36 (9M) 3.3V Synchronous CY7C0853AV Dual-Port SRAM 36 (4M) 3.3V Synchronous CY7C0852AV Dual-Port SRAM 36 (2M) 3.3V Synchronous CY7C0851AV Dual-Port SRAM 36 (1M) 3.3V Synchronous CY7C0850AV Dual-Port SRAM 31 Document History Page32 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions
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