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Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV manual Counter Interrupt and Retransmit 34, 42, 43, 44

Models: CY7C0851AV CY7C0853AV CY7C0850AV CY7C0852AV

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						CY7C0850AV, CY7C0851AV
						CY7C0852AV, CY7C0853AV
Switching Waveforms (continued)
			Figure 22. Counter Interrupt and Retransmit[34, 42, 43, 44, 45]
			tCYC2
		tCH2	tCL2
CLK
	tSCM	tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL	1FFFC		1FFFD	1FFFE	1FFFF	Last_Loaded	Last_Loaded +1
ADDRESS	1FFFC		1FFFD	1FFFE	1FFFF	Last_Loaded	Last_Loaded +1
ADDRESS					tRCINT
				tSCINT	tRCINT
CNTINT

Notes

42.CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

43.CNTINT is always driven.

44.CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.

45.The mask register assumed to have the value of 1FFFFh.

Document #: 38-06070 Rev. *H

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Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV manual Counter Interrupt and Retransmit 34, 42, 43, 44

Contents

176TQFP 172FBGA Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x Cypress Semiconductor Corporation 198 Champion Court RAM Array Logic Block DiagramTrue Mirror Reg Pin Configurations Ball BGA Top View CY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Operation Description Master ResetMailbox Interrupts Address Counter and Mask Register Operations Retransmit Mask Reset OperationCounter Interrupt Mask Load Operation Cnten ADS Cntrst Mrst CLK Programmable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan Jtag Operating Range Electrical CharacteristicsMaximum Ratings Capacitance Switching Characteristics Normal Load Load Three-state Delay Load Port to Port Delays Master Reset Timing Jtag Timing Parameter Description 167/133/100 Unit Min Switching Waveforms Master Reset Bank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port Sram Package Diagrams Ball Fbga 15 x 15 x 1.25 mm Pin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion Date USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY7C0852AV, CY7C0853AV

Switching Waveforms (continued)

Figure 22. Counter Interrupt and Retransmit[34, 42, 43, 44, 45]