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Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV manual Logic Block Diagram, True, RAM Array, Mirror Reg

Models: CY7C0851AV CY7C0853AV CY7C0850AV CY7C0852AV

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Logic Block Diagram [1]

L

R

OE

OE

R/WL

R/WR

B0

L

B0

R

B1

L

B1

R

B2

L

B2

R

L

R

B3

B3

0R

CE

0L

CE

CE1L

CE1R

DQ27L–DQ35L

9

9

DQ27R–DQ35R

9

9

DQ18L–DQ26L

I/O

I/O

DQ18R–DQ26R

9

9

DQ9L–DQ17L

Control

Control

DQ9R–DQ17R

9

9

DQ0L–DQ8L

DQ0R–DQ8R

.

True

Dual-Ported

RAM Array

18

18

A0L–A17L

Mask Register

Mask Register

A0R–A17R

R

CNT/MSK

CNT/MSK

L

ADS

L

Counter/

Counter/

ADS

Address

Address

Address

Address

CNTENL

CNTEN

Register

Decode

Decode

Register

R

CNTRST

CNTRST

CLKL

L

Mirror Reg

Mirror Reg

CLKR

CNTINT

R

CNTINT

L

TMS

Reset

TDO

Interrupt

MRST

TDI

JTAG

Interrupt

INTL

Logic

INTR

Logic

TCK

Logic

Note

1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.

Document #: 38-06070 Rev. *H

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Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV manual Logic Block Diagram, True, RAM Array, Mirror Reg

Contents

176TQFP 172FBGA Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x Cypress Semiconductor Corporation 198 Champion Court RAM Array Logic Block DiagramTrue Mirror Reg Pin Configurations Ball BGA Top View CY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Operation Description Master ResetMailbox Interrupts Address Counter and Mask Register Operations Retransmit Mask Reset OperationCounter Interrupt Mask Load Operation Cnten ADS Cntrst Mrst CLK Programmable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan Jtag Operating Range Electrical CharacteristicsMaximum Ratings Capacitance Switching Characteristics Normal Load Load Three-state Delay Load Port to Port Delays Master Reset Timing Jtag Timing Parameter Description 167/133/100 Unit Min Switching Waveforms Master Reset Bank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port Sram Package Diagrams Ball Fbga 15 x 15 x 1.25 mm Pin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion Date USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions