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Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV manual Cnten ADS Cntrst Mrst, Clk

Models: CY7C0851AV CY7C0853AV CY7C0850AV CY7C0852AV

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Figure 4. Counter, Mask, and Mirror Logic Block Diagram [1]

CNT/MSK

CNTEN

ADS

CNTRST

MRST

Bidirectional

Address

Lines

CLK

Decode

Logic

Mask

Register

Counter/

Address

Register

Address

Decode

RAM Array

	From	17	Load/Increment
	From	17
	Address	Mirror		Counter
	Lines	Mirror	1	Counter	To Readback
	Lines		1		To Readback
			1		and Address
			0		Decode
	From	17	0		Decode
			0

	Mask	Increment
	Register	Logic	Wrap		17

From	17	17
From
Mask	17	Bit 0
From		Bit 0
		+1	Wrap

Counter				Wrap
Counter		1	Detect	Wrap
		0
		+2	17
		1	17	To
				To
		0		Counter

Document #: 38-06070 Rev. *H

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Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV manual Cnten ADS Cntrst Mrst, Clk

Contents

176TQFP 172FBGA Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x Cypress Semiconductor Corporation 198 Champion Court RAM Array Logic Block DiagramTrue Mirror Reg Pin Configurations Ball BGA Top View CY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Mailbox Interrupts Master ResetOperation Description Address Counter and Mask Register Operations Retransmit Mask Reset OperationCounter Interrupt Mask Load Operation Cnten ADS Cntrst Mrst CLK Programmable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan Jtag Operating Range Electrical CharacteristicsMaximum Ratings Capacitance Switching Characteristics Normal Load Load Three-state Delay Load Port to Port Delays Master Reset Timing Jtag Timing Parameter Description 167/133/100 Unit Min Switching Waveforms Master Reset Bank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port Sram Package Diagrams Ball Fbga 15 x 15 x 1.25 mm Pin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion Date Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB