CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H Page 14 of 32
Figure 6. AC Test Load and Waveforms
Switching Characteristics Over the Operating Range
Parameter Description
-167 -133 -100
Unit
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0853AV CY7C0853AV
Min Max Min Max Min Max Min Max
fMAX2 Maximum Operating Frequency 167 133 133 100 MHz
tCYC2 Clock Cycle Time 6.0 7.5 7.5 10.0 ns
tCH2 Clock HIGH Time 2.7 3.0 3.0 4.0 ns
tCL2 Clock LOW Time 2.7 3.0 3.0 4.0 ns
tR[19] Clock Rise Time 2.0 2.0 2.0 3.0 ns
tF[19] Clock Fall Time 2.0 2.0 2.0 3.0 ns
tSA Address Setup Time 2.3 2.5 2.5 3.0 ns
tHA Address Hold Time 0.6 0.6 0.6 0.6 ns
tSB Byte Select Setup Time 2.3 2.5 2.5 3.0 ns
tHB Byte Select Hold Time 0.6 0.6 0.6 0.6 ns
tSC Chip Enable Setup Time 2.3 2.5 NA NA ns
tHC Chip Enable Hold Time 0.6 0.6 NA NA ns
tSW R/W Setup Time 2.3 2.5 2.5 3.0 ns
tHW R/W Hold Time 0.6 0.6 0.6 0.6 ns
tSD Input Data Setup Time 2.3 2.5 2.5 3.0 ns
tHD Input Data Hold Time 0.6 0.6 0.6 0.6 ns
tSAD ADS Setup Time 2.3 2.5 NA NA ns
tHAD ADS Hold Time 0.6 0.6 NA NA ns
tSCN CNTEN Setup Time 2.3 2.5 NA NA ns
tHCN CNTEN Hold Time 0.6 0.6 NA NA ns
tSRST CNTRST Setup Time 2.3 2.5 NA NA ns
tHRST CNTRST Hold Time 0.6 0.6 NA NA ns
tSCM CNT/MSK Setup Time 2.3 2.5 NA NA ns
tHCM CNT/MSK Hold Time 0.6 0.6 NA NA ns
R1 = 590 Ω
R2 = 435 Ω
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0V
VSS
90%
10%
<2ns <2ns
ALL INPUT PULSES
3.3V
VTH = 1.5V
R = 50Ω
Z0 = 50Ω
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
Note
19.Except JTAG signals (tr and tf < 10 ns [max.]).
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