CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H Page 23 of 32
Figure 19. Counter Reset[32, 33]
Switching Waveforms (continued)
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT
AnAmAp
Ax01AnAmAp
Q1Qn
Q0
D0
tCH2 tCL2
tCYC2
tSA tHA
tSW tHW
tSRST tHRST
tSD tHD
tCD2 tCD2
tCKLZ
[34]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS AnADDRESS Am
READ
Notes
32.CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
33.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
34.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
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