CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H Page 15 of 32
tOE Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns
tOLZ[20, 21] OE to Low Z 0 0 0 0 ns
tOHZ[20, 21] OE to High Z 04.004.404.705.0ns
tCD2 Clock to Data Valid 4.0 4.4 4.7 5.0 ns
tCA2 Clock to Counter Address Valid 4.0 4.4 NA NA ns
tCM2 Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns
tDC Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns
tCKHZ[20, 21] Clock HIGH to Output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
tCKLZ[20, 21] Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
tSINT Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
tRINT Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
tSCINT Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns
tRCINT Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
tCCS Clock to Clock Skew 5.2 6.0 6.0 8.0 ns
Master Reset Timing
tRS Master Reset Pulse Width 7.0 7.5 7.5 10.0 ns
tRSS Master Reset Setup Time 6.0 6.0 6.0 8.5 ns
tRSR Master Reset Recovery Time 6.0 7.5 7.5 10.0 ns
tRSF Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns
tRSCNTINT Master Reset to Counter Interrupt Flag
Reset Time
10.0 10.0 NA NA ns
Over the Operating Range (continued)
Parameter Description
-167 -133 -100
Unit
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0853AV CY7C0853AV
Min Max Min Max Min Max Min Max
Notes
20.This parameter is guaranteed by design, but it is not production tested.
21.Test conditions used are Load 2.
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