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Cypress CY7C0850AV, CY7C0851AV, CY7C0852AV, CY7C0853AV CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

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CY7C0850AV, CY7C0851AVCY7C0852AV, CY7C0853AV

Document #: 38-06070 Rev. *H Page 3 of 32

Pin Configurations

Figure 1. 172-Ball BGA (Top View)

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ADQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R

BA0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R

CNC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC

DA2L A3L DQ35L DQ34L DQ28 L DQ16L VSS VSS DQ1 6R DQ28R DQ34R DQ35R A3R A2R

EA4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R

FVDD A6L A7L B1L VDD VSS B1R A7R A6R VDD

GOEL B2L B3L CE0L CY7C0850AV

CY7C0851AV

CY7C0852AV

CE0R B3R B2R OER

HVSS R/WLA8LCLKL CLKR A8R R/WR VSS

JA9L A 10L VSS ADSL VSS VDD ADSR MRST A10R A9R

KA11L A12L A15L[2] CNTRSTL VDD VDD VSS VDD CNTRSTR A15R[2] A12R A11R

LCNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR

MA16L[2] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[2]

NDQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R

PDQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R

Note

2. For CY7C0851AV, pins M1 and M14 are NC. For CY7C0850AV, pins K3, K12 M1, and M14 are NC

[+] Feedback

Contents

Main FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM CY7C0850AV, CY7C0851AV Features Functional Description CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Logic Block Diagram CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Pin Configurations CY7C0851AV CY7C0852AV Pin Configurations CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Figure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View) Pin Configurations CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Master Reset Mailbox Interrupts CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Address Counter and Mask Register Operations Counter Reset Operation Counter Load Operation Counter Readback Operation Counter Interrupt Retransmit Mask Reset Operation Mask Load Operation Mask Readback Operation Page Page IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP Reset Maximum Ratings Operating Range Electrical Characteristics Capacitance Page Switching Characteristics JTAG Timing Switching Waveforms Figure 8. Master Reset Figure 9. Read Cycle Figure 10. Bank Select Read Figure 11. Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31] Figure 12. Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31] Figure 13. Read with Address Counter Advance Figure 14. Write with Address Counter Advance Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write Figure 16. Disabled-to-Write-to-Read-to-Write-to-Read Figure 17. Disabled-to-Read-to-Disabled-to-Write Figure 18. Read-to-Readback-to-Read-to-Read (R/W = HIGH) Figure 19. Counter Reset Figure 20. Readback State of Address Counter or Mask Register A A n+3 A Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read[39, 40, 41] L_PORT R_PORT Figure 22. Counter Interrupt and Retransmit[34, 42, 43, 44, 45] Figure 23. MailBox Interrupt Timing H X L H X High-Z Outputs Disabled LLHHD Ordering Information 256K 32K 64K Page Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions