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Cypress CY7C0850AV, CY7C0851AV, CY7C0852AV, CY7C0853AV Figure 23. MailBox Interrupt Timing, H X L H X High-Z Outputs Disabled, LLHHD

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Document #: 38-06070 Rev. *H Page 27 of 32

Figure 23. MailBox Interrupt Timing[46, 47, 48, 49, 50]

Table 7. Read/Write and Enable Operation (Any Port) [1, 8, 51, 52]Inputs Outputs OperationOE CLK CE0CE1R/W DQ0 – DQ35X H X X High-Z DeselectedX X L X High-Z DeselectedXLHLD

IN Write

LLHHD

OUT Read

H X L H X High-Z Outputs Disabled

Switching Waveforms (continued)

t

CH2

t

CL2

t

CYC2

CLK

L

tCH2 tCL2

tCYC2

CLKR

3FFFF

tSA tHA

An+3

AnAn+1 An+2

L_PORT

ADDRESS

AmAm+4

Am+1 3FFFF Am+3

R_PORT

ADDRESS

INTR

tSA tHA

tSINT

tRINT

Notes

46.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

47.Address “3FFFF” is the mailbox location for R_Port of a 9M device.

48.L_Port is configured for Write operation, and R_Port is configured for Read operation.

49.At least one byte enable (B0 – B3) is required to be active during interrupt operations.

50.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.

51.OE is an asynchronous input signal.

52.When CE changes state, deselection and Read happen after one cycle of latency.

[+] Feedback

Contents

Main FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM CY7C0850AV, CY7C0851AV Features Functional Description CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Logic Block Diagram CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Pin Configurations CY7C0851AV CY7C0852AV Pin Configurations CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Figure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View) Pin Configurations CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Master Reset Mailbox Interrupts CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Address Counter and Mask Register Operations Counter Reset Operation Counter Load Operation Counter Readback Operation Counter Interrupt Retransmit Mask Reset Operation Mask Load Operation Mask Readback Operation Page Page IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP Reset Maximum Ratings Operating Range Electrical Characteristics Capacitance Page Switching Characteristics JTAG Timing Switching Waveforms Figure 8. Master Reset Figure 9. Read Cycle Figure 10. Bank Select Read Figure 11. Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31] Figure 12. Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31] Figure 13. Read with Address Counter Advance Figure 14. Write with Address Counter Advance Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write Figure 16. Disabled-to-Write-to-Read-to-Write-to-Read Figure 17. Disabled-to-Read-to-Disabled-to-Write Figure 18. Read-to-Readback-to-Read-to-Read (R/W = HIGH) Figure 19. Counter Reset Figure 20. Readback State of Address Counter or Mask Register A A n+3 A Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read[39, 40, 41] L_PORT R_PORT Figure 22. Counter Interrupt and Retransmit[34, 42, 43, 44, 45] Figure 23. MailBox Interrupt Timing H X L H X High-Z Outputs Disabled LLHHD Ordering Information 256K 32K 64K Page Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions