CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Switching Waveforms (continued)
Figure 23. MailBox Interrupt Timing[46, 47, 48, 49, 50]
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tCH2 | tCL2 |
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CLKL |
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L_PORT | 3FFFF | An | |
ADDRESS | |||
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An+1 |
An+2 | An+3 |
INTR |
tCYC2 
tCH2 tCL2
CLKR
tSA tHA
tRINT
R_PORT | Am |
ADDRESS |
Am+1 |
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Table 7. Read/Write and Enable Operation (Any Port) [1, 8, 51, 52]
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| CE0 | CE1 | R/W | DQ0 – DQ35 | ||||
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| X |
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| H | X | X | Deselected | |
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| X |
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| X | L | X | Deselected | |
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| X |
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| L | H | L | DIN | Write |
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| L | H | H | DOUT | Read |
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Notes
46.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
47.Address “3FFFF” is the mailbox location for R_Port of a 9M device.
48.L_Port is configured for Write operation, and R_Port is configured for Read operation.
49.At least one byte enable (B0 – B3) is required to be active during interrupt operations.
50.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
51.OE is an asynchronous input signal.
52.When CE changes state, deselection and Read happen after one cycle of latency.
Document #: | Page 27 of 32 |
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