Cypress CY7C1425JV18 manuals
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Cypress CY7C1425JV18 Manual
26 pages 643.48 Kb
36-Mbit QDR-II SRAM 2-Word Burst ArchitectureCY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18Features Configurations Functional Description Selection Guide 2 CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18Document #: 001-12561 Rev. *D Page 2 of 26 Logic Block Diagram (CY7C1410JV18) Logic Block Diagram (CY7C1425JV18)Document #: 001-12561 Rev. *D Page 3 of 26 3 Logic Block Diagram (CY7C1412JV18)Logic Block Diagram (CY7C1414JV18) 4 CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18Pin Configuration165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 5 CY7C1410JV18, CY7C1425JV187 CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV188 CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18Functional OverviewRead Operations Write Operations Byte Write Operations Single Clock Mode Concurrent Transactions Depth Expansion Programmable Impedance Echo Clocks DLL 9 Application ExampleSRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) 10 CY7C1410JV18, CY7C1425JV18Truth Table Write Cycle Descriptions 12 CY7C1412JV18, CY7C1414JV18IEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Test Data-Out (TDO) Performing a TAP Reset TAP Registers TAP Instruction Set 14 CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV1818 CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18Boundary Scan Order Power Up Sequence in QDR-II SRAM 19 VVPower Up Sequence DLL Constraints Power Up Waveforms / 25 CY7C1410JV18, CY7C1425JV18Document #: 001-12561 Rev. *D Page 25 of 26 Package DiagramFigure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 26 Document History Page
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