Cypress CY7C1425JV18 Document History, REV ECN no Issue ORIG. Description of Change Date, Vkn

CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Document History Page

Document Title: CY7C1410JV18/CY7C1425JV18/CY7C1412JV18/CY7C1414JV18, 36-Mbit QDR™-II SRAM 2-Word

Burst Architecture

Document Number: 001-12561

REV.	ECN NO.	ISSUE	ORIG. OF	DESCRIPTION OF CHANGE
		DATE	CHANGE
**	808457	See ECN	VKN	New Data Sheet
*A	1061960	See ECN	VKN	Removed 300MHz speed bin
*B	1397384	See ECN	VKN	Added 267MHz speed bin
*C	1462587	See ECN	VKN/AESA	Converted from preliminary to final
				Removed 200MHz speed bin
				Updated IDD/ISB specs
				Changed DLL minimum operating frequency from 80MHz to 120MHz
				Changed tCYC max spec to 8.4ns for all speed bins
*D	2189567	See ECN	VKN/AESA	Minor Change-Moved to the external web

© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document #: 001-12561 Rev. *D Revised March 10, 2007 Page 26 of 26

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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