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Cypress CY7C1410JV18, CY7C1412JV18, CY7C1414JV18, CY7C1425JV18 TAP Controller Block Diagram, TAP Electrical Characteristics

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CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Document #: 001-12561 Rev. *D Page 15 of 26

TAP Controller Block DiagramTAP Electrical Characteristics

Over the Operating Range [10, 11, 12]

Parameter Description Test Conditions Min Max Unit

VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V

VOH2 Output HIGH Voltage IOH = −100 μA1.6 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V

VOL2 Output LOW Voltage IOL = 100 μA0.2V

VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.35VDD V

IXInput and Output Load Current GND ≤ VI ≤ VDD –5 5 μA

0

012..29

3031

Boundary Scan Register

Identification Register

012..

.

.108

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Co ntro ller

TDI TDO

TCK

TMS

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).

12.All Voltage referenced to Ground.

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Contents

Main 36-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Features Configurations Functional Description CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 2 of 26 Logic Block Diagram (CY7C1410JV18) Logic Block Diagram (CY7C1425JV18) Document #: 001-12561 Rev. *D Page 3 of 26 Logic Block Diagram (CY7C1412JV18) Logic Block Diagram (CY7C1414JV18) CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1410JV18, CY7C1425JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout Pin Definitions CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Pin Definitions CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example SRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) CY7C1410JV18, CY7C1425JV18 Truth Table Write Cycle Descriptions Page CY7C1412JV18, CY7C1414JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence DLL Constraints Power Up Waveforms Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document #: 001-12561 Rev. *D Page 23 of 26 Switching Waveforms Figure 3. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 Ordering Information CY7C1410JV18, CY7C1425JV18 Document #: 001-12561 Rev. *D Page 25 of 26 [+] Feedback Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 Document History Page