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Cypress CY7C1410JV18, CY7C1412JV18, CY7C1414JV18, CY7C1425JV18 Ordering Information

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CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Document #: 001-12561 Rev. *D Page 24 of 26

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

267 CY7C1410JV18-267BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1425JV18-267BZC

CY7C1412JV18-267BZC

CY7C1414JV18-267BZC

CY7C1410JV18-267BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1425JV18-267BZXC

CY7C1412JV18-267BZXC

CY7C1414JV18-267BZXC

CY7C1410JV18-267BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1425JV18-267BZI

CY7C1412JV18-267BZI

CY7C1414JV18-267BZI

CY7C1410JV18-267BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1425JV18-267BZXI

CY7C1412JV18-267BZXI

CY7C1414JV18-267BZXI

250 CY7C1410JV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1425JV18-250BZC

CY7C1412JV18-250BZC

CY7C1414JV18-250BZC

CY7C1410JV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1425JV18-250BZXC

CY7C1412JV18-250BZXC

CY7C1414JV18-250BZXC

CY7C1410JV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1425JV18-250BZI

CY7C1412JV18-250BZI

CY7C1414JV18-250BZI

CY7C1410JV18-250BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1425JV18-250BZXI

CY7C1412JV18-250BZXI

CY7C1414JV18-250BZXI

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Contents

Main 36-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Features Configurations Functional Description CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 2 of 26 Logic Block Diagram (CY7C1410JV18) Logic Block Diagram (CY7C1425JV18) Document #: 001-12561 Rev. *D Page 3 of 26 Logic Block Diagram (CY7C1412JV18) Logic Block Diagram (CY7C1414JV18) CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1410JV18, CY7C1425JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout Pin Definitions CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Pin Definitions CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example SRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) CY7C1410JV18, CY7C1425JV18 Truth Table Write Cycle Descriptions Page CY7C1412JV18, CY7C1414JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence DLL Constraints Power Up Waveforms Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document #: 001-12561 Rev. *D Page 23 of 26 Switching Waveforms Figure 3. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 Ordering Information CY7C1410JV18, CY7C1425JV18 Document #: 001-12561 Rev. *D Page 25 of 26 [+] Feedback Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 Document History Page