Cypress CY7C1412JV18 Logic Block Diagram CY7C1410JV18, Logic Block Diagram CY7C1425JV18, Doff

CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Logic Block Diagram (CY7C1410JV18)

8

D[7:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
NWS
	[1:0]

	Write		Write
	Reg		Reg
Decode	2M x		2M x	Decode
Write Add.	8 Array		8 Array	Read Add.
	Read Data Reg.
		16	8
					Reg.
			8
					Reg.

Address

Register

Control

Logic

Reg.

21A(20:0)

RPS

C

C

CQ

8 CQ

8 8 Q[7:0]

Logic Block Diagram (CY7C1425JV18)

9

D[8:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
BWS
	[0]

	Write		Write
	Reg		Reg
Decode	2M x		2M x	Decode
Write Add.	9 Array		9 Array	Read Add.
	Read Data Reg.
		18	9
					Reg.
			9
					Reg.

Address

Register

Control

Logic

Reg.

21A(20:0)

RPS

C

C

CQ

9 CQ

9 9 Q[8:0]

Document #: 001-12561 Rev. *D Page 2 of 26

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