Cypress CY7C1425JV18, CY7C1410JV18, CY7C1412JV18 manual Pin Definitions, Pin Name Pin Description

CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Pin Definitions

Pin Name

IO

Pin Description

D[x:0]

Input-

Data Input Signals. Sampled on the rising edge of K and

clocks during valid write operations.

K

Synchronous

CY7C1410JV18 - D[7:0]

CY7C1425JV18 - D[8:0]

CY7C1412JV18 - D[17:0]

CY7C1414JV18 - D[35:0]

Input-

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

WPS

Synchronous

write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].

0,

Nibble Write Select 0, 1 − Active LOW (CY7C1410JV18 Only). Sampled on the rising edge of the K

NWS

NWS1

and K clocks during Write operations. Used to select which nibble is written into the device during the

current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D[3:0] and

NWS1 controls D[7:4].

All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

0,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

clocks during

BWS

K

BWS1,

Synchronous

write operations. Used to select which byte is written into the device during the current portion of the write

BWS2,

operations. Bytes not written remain unaltered.

BWS3

CY7C1425JV18 − BWS0

controls D[8:0]

CY7C1412JV18 − BWS0

controls D[8:0],

BWS

1 controls D[17:9]

.

CY7C1414JV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls

D[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

Address Inputs. Sampled on the rising edge of the K (Read address) and

(Write address) clocks during

K

Synchronous

active read and write operations. These address inputs are multiplexed for both read and write operations.

Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1410JV18, 4M x 9 (2

arrays each of 2M x 9) for CY7C1425JV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1412JV18 and

1M x 36 (2 arrays each of 512K x 36) for CY7C1414JV18. Therefore, only 21 address inputs are needed

to access the entire memory array of CY7C1410JV18 and CY7C1425JV18, 20 address inputs for

CY7C1412JV18 and 19 address inputs for CY7C1414JV18. These inputs are ignored when the appro-

priate port is deselected.

Q[x:0]

Outputs-

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is

Synchronous

driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single

clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.

CY7C1410JV18 − Q[7:0]

CY7C1425JV18 − Q[8:0]

CY7C1412JV18 − Q[17:0]

CY7C1414JV18 − Q[35:0]

Input-

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

RPS

Synchronous

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is

allowed to complete and the output drivers are automatically tri-stated following the next rising edge of

the C clock. Each read access consists of a burst of two sequential transfers.

CInput Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 9 for further details.

CInput Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 9 for further details.

K	Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
	and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
	edge of K.

KInput Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode.

Document #: 001-12561 Rev. *D Page 6 of 26

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