CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Document #: 001-12561 Rev. *D Page 22 of 26
Switching Characteristics
Over the Operating Range [19, 20]
Cypress
Parameter Consortium
Parameter Description 267 MHz 250 MHz Unit
Min Max Min Max
tPOWER VDD(Typical) to the first access [21] 11ms
tCYC tKHKH K Clock and C Clock Cycle Time 3.75 8.4 4.0 8.4 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 1.5–1.6– ns
tKL tKLKH Input Clock (K/K and C/C) LOW 1.5 – 1.6 – ns
tKHKHtKHKHK Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.68 – 1.8 – ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0 1.68 0 1.8 ns
Setup Times
tSA tAVKH Address Setup to K Clock Rise 0.3 –0.35– ns
tSC tIVKH Control Setup to K Clock Rise (RPS, WPS) 0.3–0.35– ns
tSCDDR tIVKH DDR Control Setup to Clock (K/K) Rise (BWS0, BWS1, BWS3, BWS4) 0.3 –0.35– ns
tSD tDVKH D[X:0] Setup to Clock (K/K) Rise 0.3–0.35– ns
Hold Times
tHA tKHAX Address Hold after K Clock Rise 0.3 – 0.35 – ns
tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.3–0.35– ns
tHCDDR tKHIX DDR Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS3,BWS4) 0.3 –0.35– ns
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.3 – 0.35 – ns
Output Times
tCO tCHQV C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid – 0.45 – 0.45 ns
tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) –0.45 – – 0.45 – ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock Rise –0.45 – –0.45 – ns
tCQD tCQHQV Echo Clock High to Data Valid – 0.27 – 0.30 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.27 – –0.30 – ns
tCQH tCQHCQL Output Clock (CQ/CQ) HIGH [22] 1.43 – 1.55 – ns
tCQHCQHtCQHCQHCQ Clock Rise to CQ Clock Rise (rising edge to rising edge) [22] 1.43 – 1.55 – ns
tCHZ tCHQZ Clock (C/C) Rise to High-Z (Active to High-Z) [23, 24] – 0.45 – 0.45 ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z [23, 24] –0.45 – –0.45 – ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – Cycles
tKC Reset tKC Reset K Static to DLL Reset 30 – 30 – ns
Notes
20.When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
21.This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.
22.These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.
23.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 21. Transition is measured ± 100 mV from steady
state voltage.
24.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
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