Cypress CY7C1916CV18 manuals
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Cypress CY7C1916CV18 Manual
29 pages 681.26 Kb
18-Mbit DDR-II SRAM 2-Word Burst ArchitectureCY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18Features Configurations Functional Description Selection Guide 2 CY7C1318CV18, CY7C1320CV18Document Number: 001-07160 Rev. *E Page 2 of 29 Logic Block Diagram (CY7C1316CV18) Logic Block Diagram (CY7C1916CV18)1M x 8 Array 1M x 8 Array 1M x 9 Array 1M x 9 Array 3 CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18Logic Block Diagram (CY7C1318CV18) Logic Block Diagram (CY7C1320CV18)512K x 18 Array 512K x 18 Array 256K x 36 Array 256K x 36 Array 4 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 5 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 6 CY7C1316CV18, CY7C1916CV187 CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV188 CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18Functional OverviewRead Operations Write Operations Byte Write Operations Single Clock Mode DDR Operation Depth Expansion Programmable Impedance 9 CY7C1316CV18, CY7C1916CV18Echo Clocks DLL Application Example 12 IEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Test Data-Out (TDO) Performing a TAP Reset TAP Registers TAP Instruction Set 13 CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV1816 CY7C1316CV18, CY7C1916CV1818 CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV1819 CY7C1316CV18, CY7C1916CV18Power Up Sequence in DDR-II SRAM VVPower Up Sequence DLL Constraints / 20 CY7C1318CV18, CY7C1320CV18
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