CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Features
Configurations
Functional Description
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Logic Block Diagram CY7C1316CV18
Logic Block Diagram CY7C1916CV18
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CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Logic Block Diagram CY7C1318CV18
Logic Block Diagram CY7C1320CV18
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CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Pin Configuration
165-Ball FBGA 13 x 15 x 1.4 mm Pinout
165-Ball FBGA 13 x 15 x 1.4 mm Pinout
Pin Configuration continued
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Pin Definitions
CY7C1318CV18, CY7C1320CV18
CY7C1316CV18, CY7C1916CV18
CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
Pin Definitions continued
Read Operations
Single Clock Mode
Functional Overview
Write Operations
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Application Example
Echo Clocks
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Burst Address Table
Write Cycle Descriptions
Truth Table
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Write Cycle Descriptions
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Write Cycle Descriptions
Test Mode Select TMS
Disabling the JTAG Feature
Test Access Port-Test Clock
Performing a TAP Reset
SAMPLE/PRELOAD
IDCODE
SAMPLE Z
BYPASS
Page 14 of
TAP Controller State Diagram
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Instruction Codes
Identification Register Definitions
Scan Register Sizes
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Boundary Scan Order
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
DLL Constraints
Power Up Sequence in DDR-II SRAM
Power Up Sequence
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Maximum Ratings
Electrical Characteristics
DC Electrical Characteristics
Operating Range
DC Electrical Characteristics
Electrical Characteristics continued
AC Electrical Characteristics
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Capacitance
Thermal Resistance
Package
Parameter
Switching Characteristics
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Switching Characteristics continued
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
READ
Switching Waveforms
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
tCQDOH
Ordering Information
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Ordering Information continued
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Figure 6. 165-Ball FBGA 13 x 15 x 1.4 mm
Package Diagram
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
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