Cypress manual CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18, + Feedback

CY7C1316CV18, CY7C1916CV18

CY7C1318CV18, CY7C1320CV18

Logic Block Diagram (CY7C1316CV18)

20

A(19:0)

LD

K

K

DOFF

VREF

R/W

NWS[1:0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
Decode	Reg	Reg	Decode
	1M x	1M x			8
WriteAdd.	8Array	8Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

16
8	Reg.		Reg.	8		CQ
						CQ
8					8
	Reg.	8				DQ[7:0]

Logic Block Diagram (CY7C1916CV18)

20

A(19:0)

LD

K

K

DOFF

VREF

R/W

BWS[0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
Decode	Reg	Reg	Decode
	1M x	1M x			9
WriteAdd.	9Array	9Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

18
9	Reg.		Reg.	9		CQ
						CQ
9					9
	Reg.	9				DQ[8:0]

Document Number: 001-07160 Rev. *E Page 2 of 29

[+] Feedback