Configurations
Features
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Functional Description
Logic Block Diagram CY7C1916CV18
Logic Block Diagram CY7C1316CV18
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
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Logic Block Diagram CY7C1320CV18
Logic Block Diagram CY7C1318CV18
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
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165-Ball FBGA 13 x 15 x 1.4 mm Pinout
Pin Configuration
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Pin Configuration continued
165-Ball FBGA 13 x 15 x 1.4 mm Pinout
CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
Pin Definitions
Pin Definitions continued
CY7C1318CV18, CY7C1320CV18
CY7C1316CV18, CY7C1916CV18
Read Operations
Functional Overview
Write Operations
Byte Write Operations
Echo Clocks
Application Example
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
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Truth Table
Write Cycle Descriptions
Burst Address Table
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Write Cycle Descriptions
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Write Cycle Descriptions
Test Access Port-Test Clock
Disabling the JTAG Feature
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan JTAG
SAMPLE Z
IDCODE
SAMPLE/PRELOAD
BYPASS
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
TAP Controller State Diagram
Page 14 of
TAP Electrical Characteristics
TAP Controller Block Diagram
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
TAP Timing and Test Conditions
TAP AC Switching Characteristics
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Scan Register Sizes
Identification Register Definitions
Instruction Codes
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Boundary Scan Order
Power Up Sequence
Power Up Sequence in DDR-II SRAM
DLL Constraints
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
DC Electrical Characteristics
Electrical Characteristics
Maximum Ratings
Operating Range
AC Electrical Characteristics
Electrical Characteristics continued
DC Electrical Characteristics
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Thermal Resistance
Capacitance
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Package
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Switching Characteristics
Parameter
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Switching Characteristics continued
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Switching Waveforms
READ
tCQDOH
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Ordering Information
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Ordering Information continued
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18
Package Diagram
Figure 6. 165-Ball FBGA 13 x 15 x 1.4 mm
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