ST & T UPSD3212CV manuals

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ST & T UPSD3212CV Manual

ST & T UPSD3212CV Manual

163 pages2.2 Mb

uPSD3212A, uPSD3212C uPSD3212CV
- Flash Programmable System Devices with 8032 MCU with USB and P r ogrammable Logic
  - FEATURES SUMMARY
    - 2uPSD3212A, uPSD3212C, uPSD3212CV
      - Table 1. Device Summary
  - 3TABLE OF CONTENTS
  - 7SUMMARY DESCRIPTION
    - 8Figure 3. TQFP52 Connections
    - 9Figure 4. TQFP80 Connections
    - 10Table 2. 80-Pin Package Pin Description
    - uPSD3212A, uPSD3212C, uPSD3212CV
  - 1252-PIN PACKAGE I/O PORT
  - 13ARCHITECTURE OVERVIEW
    - 19Table 5. Logical Instructions
    - 21uPSD3212A, uPSD3212C, uPSD3212CV
      - 26Figure 14. State Sequence in uPSD321x Devices
  - 27uPSD3200 HARDWARE DESCRIPTION
  - 28MCU MODULE DISCRIPTION
    - 29Table 16. List of all SFR
    - 32uPSD3212A, uPSD3212C, uPSD3212CV
      - Table 17. PSD Module Register Address Offset
  - 34INTERRUPT SYSTEM
    - 35Figure 16. Interrupt System
    - 37Table 20. Description of the IE Bits.
    - Table 21. Description of the IEA Bits
    - Table 22. Description of the IP Bits
  - 39POWER-SAVING MODE
  - 40I/O PORTS (MCU MODULE)
    - 42PORT Type and Description Figure 17. PORT Type and Description (Part 1)
    - 43Figure 18. PORT Type and Description (Part 2)
      - pull-ups
        +
  - 44OSCILLATOR
  - 45SUPERVISORY
  - 46WATCHDOG TIMER
  - 48TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIM ER 2)
    - 49Table 39. Description of the TMOD Bits
    - 52Table 41. Timer/Counter 2 Operating Modes
    - Table 42. Description of the T2CON Bits
    - 53Figure 24. Timer 2 in Capture Mode
    - Figure 25. Timer 2 in Auto-Reload Mode
  - 55STANDARD SERIAL INTERFACE (UART)
    - 56Table 43. Serial Port Control Register (SCON)
      - 76543210 SM0 SM1 SM2 REN TB8 RB8 TI RI
    - 57Table 44. Description of the SCON Bits
    - 61Figure 29. Serial Port Mode 1, Block Diagram
    - Figure 30. Serial Port Mode 1, Waveforms
      - 63/163
    - 63Figure 31. Serial Port Mode 2, Block Diagram
    - Figure 32. Serial Port Mode 2, Waveforms
    - 64Figure 33. Serial Port Mode 3, Block Diagram
    - Figure 34. Serial Port Mode 3, Waveforms
  - 65ANALOG-TO-DIGITAL CO N VERTOR (ADC)
    - 66Table 46. ADC SFR Memory Map
    - Table 47. Description of the ACON Bits
    - Table 48. ADC Clock Input
  - 67PULSE WIDTH MODULATION (PWM)
    - 68Figure 36. Four-Channel 8-bit PWM Block Diagram
  - 72I2C INTERFACE
    - 73Table 51. Description of the S2CON Bits
    - Table 52. Selection of the Serial Clock Frequency SCL in Master Mode
  - 76USB HARDWARE
    - 77Table 62. USB Interrupt Enable Register (UIEN: 0E9h) Table 63. Description of the UIEN Bits
    - 78Table 64. USB Interrupt Status Register (UISTA: 0E8h) Table 65. Description of the UISTA Bits
    - 81Table 70. USB Control Register (UCON2: 0ECh) Table 71. Description of the UCON2 Bits
    - Table 72. USB Endpoint0 Status Register (USTA: 0EDh) Table 73. Description of the USTA Bits
    - 84Table 78. Transceiver DC Characteristics
    - Table 79. Transceiver AC Characteristics
    - 87Figure 44. Differential to EOP Transition Skew and EOP Width
    - Figure 45. Differential Data Jitter
  - 88PSD MODULE
    - concurrently.
      - 89Figure 46. PSD MODULE Block Diagram
        AI07431
  - 91DEVELOPMENT SYSTEM
  - 92PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
  - 93PSD MODULE DETAILED OPERATION
    - or
    - operation
  - MEMORY BLOCKS
  - 106PLDS
    - 107Figure 54. PLD Diagram
      - DECODE PLD
        Note: 1. Ports A is not available in the 52-pin package
      - PAGE REGISTER
      - CPLD
    - 112AN1171
  - 113I/O PORTS (PSD MODUL E)
    - 114AN1171
      - 115Figure 60. Peripheral I/O Mode
      - Table 89. Port Operating Modes
      - Table 91. I/O Port Latched Address Output Assignments
      - Table 90. Port Operating Mode Settings
  - 122POWER MANAGEMENT
    - 125Table 100. Power Management Mode Registers PMMR2
    - Table 101. APD Counter Operation
  - 126RESET TIMING AND DEVICE STATUS AT RESET
  - 127PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
    - AN1153
  - INITIAL DELIVERY STATE
  - 128AC/DC PARAMETERS
    - 129Table 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
  - 130MAXIMUM RATING
  - 131EMC CHARACTERISTICS
  - 133DC AND AC PARAMETERS
    - 134Figure 70. Switching Waveforms Key
      - AI03102
    - 135Table 113. Major Parameters
    - 136Table 114. DC Characteristics (5V Devices)
    - 138Table 115. DC Characteristics (3V Devices)
    - 140Figure 71. External Program Memory READ Cycle
    - Table 116. External Program Memory AC Characteristics (with the 5V MCU Module)
    - 141Table 117. External Program Memory AC Characteristics (with the 3V MCU Module)
    - 142Figure 72. External Data Memory READ Cycle
    - Table 118. External Clock Drive (with the 5V MCU Module)
    - Table 119. External Clock Drive (with the 3V MCU Module)
    - 143Figure 73. External Data Memory WRITE Cycle
    - Table 120. External Data Memory AC Characteristics (with the 5V MCU Module)
    - 144Table 121. External Data Memory AC Characteristics (with the 3V MCU Module)
    - Table 122. A/D Analog Specification
    - 145Figure 74. Input to Output D isable / Enable
    - Table 123. CPLD Combinatorial Timing (5V Devices)
    - Table 124. CPLD Combinatorial Timing (3V Devices)
    - 146Figure 75. Synchronous Clock Mode Tim i ng P LD
    - Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
    - 147Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
    - Figure 76. Asynchronous RESET / Preset
    - Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)
    - 148Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
    - Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
    - 149Figure 78. Input Macrocell Ti ming (Product Term Clock)
    - Table 129. Input Macrocell Timing (5V Devices)
    - Table 130. Input Macrocell Timing (3V Devices)
    - 150Table 131. Program, WRITE and Erase Times (5V Devices)
    - Table 132. Program, WRITE and Erase Times (3V Devices)
    - 151Figure 79. Peripheral I/O READ Timing
    - Table 133. Port A Peripheral Data Mode READ Timing (5V Devices)
    - Table 134. Port A Peripheral Data Mode READ Timing (3V Devices)
    - 152Figure 80. Peripheral I/O WRIT E Timing
    - Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices)
    - Table 136. Port A Peripheral Data Mode WRITE Timing (3V Devices)
    - 153Figure 81. Reset (RESET) Timing
    - Table 137. Reset (RESET) Timing (5V Devices)
    - Table 138. Reset (RESET) Timing (3V Devices)
    - Table 139. VSTBYON Definitions Timing (5V Devices)
    - Table 140. VSTBYON Timing (3V Devices)
    - 154Figure 82. ISC Timing
    - Table 141. ISC Timing (5V Devices)
    - 155Table 142. ISC Timing (3V Devices)
    - Figure 83. MCU Module AC Measurement I/O Waveform
    - Figure 84. PSD MODULE AC Float I/O Waveform
    - 156Figure 85. External Clock Cycle
    - Figure 86. Recommended Oscillator Circui t s
    - Figure 87. PSD MODULE AC Measurement I/O Waveform Figure 88. PSD MODULEAC Measurement
    - Load Circuit
    - Table 143. Capacitance
  - 157PACKAGE MECHANICAL INFORMATIO N
    - 158Table 144. TQFP52 52-lead Plastic Thin, Quad, Flat Package Mechanical Data
    - 160Table 145. TQFP80 80-lead Plastic Thin, Quad, Flat Package Mechanical Data
  - 161PART NUMBERING
    - Table 146. Ordering Information Scheme
  - 162REVISION HISTORY
    - Table 147. Document Revision History
      - 163163/163

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