Main
uPSD3212A, uPSD3212C uPSD3212CV
Flash Programmable System Devices with 8032 MCU with USB and P r ogrammable Logic
FEATURES SUMMARY
uPSD3212A, uPSD3212C, uPSD3212CV
Table 1. Device Summary
TABLE OF CONTENTS
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SUMMARY DESCRIPTION
Figure 3. TQFP52 Connections
Figure 4. TQFP80 Connections
Table 2. 80-Pin Package Pin Description
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uPSD3212A, uPSD3212C, uPSD3212CV
52-PIN PACKAGE I/O PORT
ARCHITECTURE OVERVIEW
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Table 5. Logical Instructions
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uPSD3212A, uPSD3212C, uPSD3212CV
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Figure 14. State Sequence in uPSD321x Devices
uPSD3200 HARDWARE DESCRIPTION
MCU MODULE DISCRIPTION
Table 16. List of all SFR
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uPSD3212A, uPSD3212C, uPSD3212CV
Table 17. PSD Module Register Address Offset
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INTERRUPT SYSTEM
Figure 16. Interrupt System
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Table 20. Description of the IE Bits.
Table 21. Description of the IEA Bits
Table 22. Description of the IP Bits
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POWER-SAVING MODE
I/O PORTS (MCU MODULE)
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PORT Type and Description Figure 17. PORT Type and Description (Part 1)
Figure 18. PORT Type and Description (Part 2)
pull-ups
+
OSCILLATOR
SUPERVISORY
WATCHDOG TIMER
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TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIM ER 2)
Table 39. Description of the TMOD Bits
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Table 41. Timer/Counter 2 Operating Modes
Table 42. Description of the T2CON Bits
Figure 24. Timer 2 in Capture Mode
Figure 25. Timer 2 in Auto-Reload Mode
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STANDARD SERIAL INTERFACE (UART)
Table 43. Serial Port Control Register (SCON)
76543210 SM0 SM1 SM2 REN TB8 RB8 TI RI
Table 44. Description of the SCON Bits
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Figure 29. Serial Port Mode 1, Block Diagram
Figure 30. Serial Port Mode 1, Waveforms
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Figure 31. Serial Port Mode 2, Block Diagram
Figure 32. Serial Port Mode 2, Waveforms
Figure 33. Serial Port Mode 3, Block Diagram
Figure 34. Serial Port Mode 3, Waveforms
ANALOG-TO-DIGITAL CO N VERTOR (ADC)
Table 46. ADC SFR Memory Map
Table 47. Description of the ACON Bits
Table 48. ADC Clock Input
PULSE WIDTH MODULATION (PWM)
Figure 36. Four-Channel 8-bit PWM Block Diagram
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I2C INTERFACE
Table 51. Description of the S2CON Bits
Table 52. Selection of the Serial Clock Frequency SCL in Master Mode
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USB HARDWARE
Table 62. USB Interrupt Enable Register (UIEN: 0E9h) Table 63. Description of the UIEN Bits
Table 64. USB Interrupt Status Register (UISTA: 0E8h) Table 65. Description of the UISTA Bits
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Table 70. USB Control Register (UCON2: 0ECh) Table 71. Description of the UCON2 Bits
Table 72. USB Endpoint0 Status Register (USTA: 0EDh) Table 73. Description of the USTA Bits
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Table 78. Transceiver DC Characteristics
Table 79. Transceiver AC Characteristics
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Figure 44. Differential to EOP Transition Skew and EOP Width
Figure 45. Differential Data Jitter
PSD MODULE
concurrently.
Figure 46. PSD MODULE Block Diagram
AI07431
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DEVELOPMENT SYSTEM
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
PSD MODULE DETAILED OPERATION
or
operation
MEMORY BLOCKS
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Table 82. Instructions
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PLDS
Figure 54. PLD Diagram
DECODE PLD
Note: 1. Ports A is not available in the 52-pin package
PAGE REGISTER
CPLD
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AN1171
I/O PORTS (PSD MODUL E)
AN1171
Figure 60. Peripheral I/O Mode
Table 89. Port Operating Modes
Table 91. I/O Port Latched Address Output Assignments
Table 90. Port Operating Mode Settings
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POWER MANAGEMENT
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Table 100. Power Management Mode Registers PMMR2
Table 101. APD Counter Operation
RESET TIMING AND DEVICE STATUS AT RESET
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
AN1153
INITIAL DELIVERY STATE
AC/DC PARAMETERS
Table 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
MAXIMUM RATING
EMC CHARACTERISTICS
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DC AND AC PARAMETERS
Figure 70. Switching Waveforms Key
AI03102
Table 113. Major Parameters
Table 114. DC Characteristics (5V Devices)
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Table 115. DC Characteristics (3V Devices)
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Figure 71. External Program Memory READ Cycle
Table 116. External Program Memory AC Characteristics (with the 5V MCU Module)
Table 117. External Program Memory AC Characteristics (with the 3V MCU Module)
Figure 72. External Data Memory READ Cycle
Table 118. External Clock Drive (with the 5V MCU Module)
Table 119. External Clock Drive (with the 3V MCU Module)
Figure 73. External Data Memory WRITE Cycle
Table 120. External Data Memory AC Characteristics (with the 5V MCU Module)
Table 121. External Data Memory AC Characteristics (with the 3V MCU Module)
Table 122. A/D Analog Specification
Figure 74. Input to Output D isable / Enable
Table 123. CPLD Combinatorial Timing (5V Devices)
Table 124. CPLD Combinatorial Timing (3V Devices)
Figure 75. Synchronous Clock Mode Tim i ng P LD
Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
Figure 76. Asynchronous RESET / Preset
Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)
Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
Figure 78. Input Macrocell Ti ming (Product Term Clock)
Table 129. Input Macrocell Timing (5V Devices)
Table 130. Input Macrocell Timing (3V Devices)
Table 131. Program, WRITE and Erase Times (5V Devices)
Table 132. Program, WRITE and Erase Times (3V Devices)
Figure 79. Peripheral I/O READ Timing
Table 133. Port A Peripheral Data Mode READ Timing (5V Devices)
Table 134. Port A Peripheral Data Mode READ Timing (3V Devices)
Figure 80. Peripheral I/O WRIT E Timing
Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices)
Table 136. Port A Peripheral Data Mode WRITE Timing (3V Devices)
Figure 81. Reset (RESET) Timing
Table 137. Reset (RESET) Timing (5V Devices)
Table 138. Reset (RESET) Timing (3V Devices)
Table 139. VSTBYON Definitions Timing (5V Devices)
Table 140. VSTBYON Timing (3V Devices)
Figure 82. ISC Timing
Table 141. ISC Timing (5V Devices)
Table 142. ISC Timing (3V Devices)
Figure 83. MCU Module AC Measurement I/O Waveform
Figure 84. PSD MODULE AC Float I/O Waveform
Figure 85. External Clock Cycle
Figure 86. Recommended Oscillator Circui t s
Figure 87. PSD MODULE AC Measurement I/O Waveform Figure 88. PSD MODULEAC Measurement
Load Circuit
Table 143. Capacitance
PACKAGE MECHANICAL INFORMATIO N
Table 144. TQFP52 52-lead Plastic Thin, Quad, Flat Package Mechanical Data
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Table 145. TQFP80 80-lead Plastic Thin, Quad, Flat Package Mechanical Data
PART NUMBERING
Table 146. Ordering Information Scheme
REVISION HISTORY
Table 147. Document Revision History
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