ST & T UPSD3212A, UPSD3212C, UPSD3212CV - page 74

uPSD3212A, uPSD3212C, uPSD3212CV

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Serial Status Register (S2STA)

S2STA is a “Read-only” register. The contents of

this register may be used as a vector to a service

routine. This optimized the response time of the

software and consequently that of the I2C bus. The

status codes for all possible modes of the I2C bus

interface are given Table 54.

This flag is set, and an interrupt is generated, after

any of the following events occur:

1. Own slave address has been received during

AA = 1: ack_int

2. The general call address has been received

while GC(S2ADR.0) = 1 and AA = 1:

3. A data byte has been received or transmitted

in Master Mode (even if arbitration is lost):

ack_int

4. A data byte has been received or transmitted

as selected slave: ack_int

5. A stop condition is received as selected slave

receiver or transmitter: stop_int

Data Shift Register (S2DAT)

S2DAT contains the serial data to be transmitted

or data which has just been received. The MSB

(Bit 7) is transmitted or received first; that is, data

shifted from right to left.

Table 53. Serial Status Register (S2STA)

Table 54. Description of the S2STA Bits

Note: 1. Interrupt Flag Bit (INTR, S2STA Bit 5) is cleared by H ard ware as reading S2STA register.

2. I2C Interrupt Flag (INTR) can occur in below case.

Table 55. Data Shift Register (S2DAT)

76543210

GC STOP INTR TX_MODE BBUSY BLOST /ACK_REP SLV

Bit Symbol Function

7 GC General Call Flag

6 STOP Stop Flag. This bit is set when a STOP condition is rec eived

5INTR(1,2) Interrupt Flag. This bit is set when an I²C Interrupt c ondition is requested

4TX_MODE

Transmission Mode Flag.

This bit is set when the I²C is a transmitter; otherwise this bit is reset

3 BBUSY Bus Busy Flag.

This bit is set when the bus is being used by another master ; otherwise, this bit is reset

2BLOST

Bus Lost Flag.

This bit is set when the master loses the bus contention; othe rwise this bit is reset

1/ACK_REP

Acknowledge Response Flag.

This bit is set when the receiver transmits the not acknowledge signal

This bit is reset when the receiver transmits the acknowledge signal

0SLV

Slave Mode Flag.

This bit is set when the I²C plays role in the Slave Mode; otherwise this bit is reset

76543210

S2DAT7 S2DAT6 S2DAT5 S2DAT4 S2DAT3 S2DAT2 S2DAT1 S2DAT0

Contents

Main uPSD3212A, uPSD3212C uPSD3212CV Flash Programmable System Devices with 8032 MCU with USB and P r ogrammable Logic FEATURES SUMMARY uPSD3212A, uPSD3212C, uPSD3212CV Table 1. Device Summary TABLE OF CONTENTS Page Page Page SUMMARY DESCRIPTION Figure 3. TQFP52 Connections Figure 4. TQFP80 Connections Table 2. 80-Pin Package Pin Description Page uPSD3212A, uPSD3212C, uPSD3212CV 52-PIN PACKAGE I/O PORT ARCHITECTURE OVERVIEW Page Page Page Page Page Table 5. Logical Instructions Page uPSD3212A, uPSD3212C, uPSD3212CV Page Page Page Page Figure 14. State Sequence in uPSD321x Devices uPSD3200 HARDWARE DESCRIPTION MCU MODULE DISCRIPTION Table 16. List of all SFR Page Page uPSD3212A, uPSD3212C, uPSD3212CV Table 17. PSD Module Register Address Offset Page INTERRUPT SYSTEM Figure 16. Interrupt System Page Table 20. Description of the IE Bits. Table 21. Description of the IEA Bits Table 22. Description of the IP Bits Page POWER-SAVING MODE I/O PORTS (MCU MODULE) Page PORT Type and Description Figure 17. PORT Type and Description (Part 1) Figure 18. PORT Type and Description (Part 2) pull-ups + OSCILLATOR SUPERVISORY WATCHDOG TIMER Page TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIM ER 2) Table 39. Description of the TMOD Bits Page Page Table 41. Timer/Counter 2 Operating Modes Table 42. Description of the T2CON Bits Figure 24. Timer 2 in Capture Mode Figure 25. Timer 2 in Auto-Reload Mode Page STANDARD SERIAL INTERFACE (UART) Table 43. Serial Port Control Register (SCON) 76543210 SM0 SM1 SM2 REN TB8 RB8 TI RI Table 44. Description of the SCON Bits Page Page Page Figure 29. Serial Port Mode 1, Block Diagram Figure 30. Serial Port Mode 1, Waveforms Page 63/163 Figure 31. Serial Port Mode 2, Block Diagram Figure 32. Serial Port Mode 2, Waveforms Figure 33. Serial Port Mode 3, Block Diagram Figure 34. Serial Port Mode 3, Waveforms ANALOG-TO-DIGITAL CO N VERTOR (ADC) Table 46. ADC SFR Memory Map Table 47. Description of the ACON Bits Table 48. ADC Clock Input PULSE WIDTH MODULATION (PWM) Figure 36. Four-Channel 8-bit PWM Block Diagram Page Page Page I2C INTERFACE Table 51. Description of the S2CON Bits Table 52. Selection of the Serial Clock Frequency SCL in Master Mode Page Page USB HARDWARE Table 62. USB Interrupt Enable Register (UIEN: 0E9h) Table 63. Description of the UIEN Bits Table 64. USB Interrupt Status Register (UISTA: 0E8h) Table 65. Description of the UISTA Bits Page Page Table 70. USB Control Register (UCON2: 0ECh) Table 71. Description of the UCON2 Bits Table 72. USB Endpoint0 Status Register (USTA: 0EDh) Table 73. Description of the USTA Bits Page Page Table 78. Transceiver DC Characteristics Table 79. Transceiver AC Characteristics Page Page Figure 44. Differential to EOP Transition Skew and EOP Width Figure 45. Differential Data Jitter PSD MODULE concurrently. Figure 46. PSD MODULE Block Diagram AI07431 Page DEVELOPMENT SYSTEM PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET PSD MODULE DETAILED OPERATION or operation MEMORY BLOCKS Page Table 82. Instructions Page Page Page Page cannot Page may Page Page Page PLDS Figure 54. PLD Diagram DECODE PLD Note: 1. Ports A is not available in the 52-pin package PAGE REGISTER CPLD Page Page Page Page AN1171 I/O PORTS (PSD MODUL E) AN1171 Figure 60. Peripheral I/O Mode Table 89. Port Operating Modes Table 91. I/O Port Latched Address Output Assignments Table 90. Port Operating Mode Settings Page Page Page Page Page Page POWER MANAGEMENT Page Page Table 100. Power Management Mode Registers PMMR2 Table 101. APD Counter Operation RESET TIMING AND DEVICE STATUS AT RESET PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE AN1153 INITIAL DELIVERY STATE AC/DC PARAMETERS Table 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) MAXIMUM RATING EMC CHARACTERISTICS Page DC AND AC PARAMETERS Figure 70. Switching Waveforms Key AI03102 Table 113. Major Parameters Table 114. DC Characteristics (5V Devices) Page Table 115. DC Characteristics (3V Devices) Page Figure 71. External Program Memory READ Cycle Table 116. External Program Memory AC Characteristics (with the 5V MCU Module) Table 117. External Program Memory AC Characteristics (with the 3V MCU Module) Figure 72. External Data Memory READ Cycle Table 118. External Clock Drive (with the 5V MCU Module) Table 119. External Clock Drive (with the 3V MCU Module) Figure 73. External Data Memory WRITE Cycle Table 120. External Data Memory AC Characteristics (with the 5V MCU Module) Table 121. External Data Memory AC Characteristics (with the 3V MCU Module) Table 122. A/D Analog Specification Figure 74. Input to Output D isable / Enable Table 123. CPLD Combinatorial Timing (5V Devices) Table 124. CPLD Combinatorial Timing (3V Devices) Figure 75. Synchronous Clock Mode Tim i ng P LD Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Figure 76. Asynchronous RESET / Preset Figure 77. Asynchronous Clock Mode Timing (Product Term Clock) Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) Figure 78. Input Macrocell Ti ming (Product Term Clock) Table 129. Input Macrocell Timing (5V Devices) Table 130. Input Macrocell Timing (3V Devices) Table 131. Program, WRITE and Erase Times (5V Devices) Table 132. Program, WRITE and Erase Times (3V Devices) Figure 79. Peripheral I/O READ Timing Table 133. Port A Peripheral Data Mode READ Timing (5V Devices) Table 134. Port A Peripheral Data Mode READ Timing (3V Devices) Figure 80. Peripheral I/O WRIT E Timing Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices) Table 136. Port A Peripheral Data Mode WRITE Timing (3V Devices) Figure 81. Reset (RESET) Timing Table 137. Reset (RESET) Timing (5V Devices) Table 138. Reset (RESET) Timing (3V Devices) Table 139. VSTBYON Definitions Timing (5V Devices) Table 140. VSTBYON Timing (3V Devices) Figure 82. ISC Timing Table 141. ISC Timing (5V Devices) Table 142. ISC Timing (3V Devices) Figure 83. MCU Module AC Measurement I/O Waveform Figure 84. PSD MODULE AC Float I/O Waveform Figure 85. External Clock Cycle Figure 86. Recommended Oscillator Circui t s Figure 87. PSD MODULE AC Measurement I/O Waveform Figure 88. PSD MODULEAC Measurement Load Circuit Table 143. Capacitance PACKAGE MECHANICAL INFORMATIO N Table 144. TQFP52 52-lead Plastic Thin, Quad, Flat Package Mechanical Data Page Table 145. TQFP80 80-lead Plastic Thin, Quad, Flat Package Mechanical Data PART NUMBERING Table 146. Ordering Information Scheme REVISION HISTORY Table 147. Document Revision History 163/163