Texas Instruments TMS320C3x manuals
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Texas Instruments TMS320C3x Manual
757 pages 2.87 Mb
Preface 3 Read This FirstAbout This Manual Notational Conventions 5 Information About CautionsRelated Documentation From Texas InstrumentsTMS320C3x/C4x Optimizing C Compiler Users Guide TMS320C3x/C4x Assembly Language Tools Users Guide TMS320C3x General Purpose Applications Users Guide If You Need Assistance TMS320C3x C Source Debugger Users Guide TMS320 DSP Development Support Reference Guide Digital Signal Processing Applications with the TMS320 Family, Vol. I. DFT/FFT and Convolution Algorithms. The Fast Fourier Transform. Digital Signal Processing Design Digital Filters: Analysis and Design TMS320 Third-Party Support Reference Guide 6 ReferencesDigital Signal Processing with the TMS320C25. 10 If You Need Assistance . . .World-Wide Web Sites North America, South America, Central America Europe, Middle East, Africa Asia-Pacific Japan 11 Trademarks12 Contents19 Figures25 Tables27 Examples30 Introduction37 Architectural Overview64 CPU Registers83 Memory and the Instruction Cache106 Data Formats and Floating-Point Operation154 Addressing Modes185 Program Flow Control237 Pipeline Operation267 TMS320C30 and TMS320C31 External-Memory Interface304 TMS320C32 Enhanced External Memory Interface380 PeripheralsChapter 12381 12.1 Timers394 12.2 Serial Ports427 12.3 DMA Controller12.3.1 DMA Functional Description 429 12.3.2 DMA Basic Operation430 Figure 1234. DMA Basic Operation431 Figure 1235. Memory-Mapped Locations for DMA Channels12-53 12.3.3.1 DMA Global-Control Register 432 Figure 1236. TMS320C30 and TMS320C31 DMA Global-Control RegisterFigure 1237. TMS320C32 DMA0 Global-Control Register Figure 1238. TMS320C32 DMA1 Global-Control Register 433 Table 126. DMA Global-Control Register Bits Summary435 Table 126. DMA Global-Control Register Bits Summary (Continued)12.3.3.2 Destination-Address and Source-Address Registers 436 Figure 1239. DMA Controller Address Generation438 Figure 1240. Transfer-Counter Operation12.3.4 CPU/DMA Interrupt-Enable Register 439 Figure 1241. TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Registerxx EDINT ETINT1 ETINT0 ERINT1 EXINT1 Notes: 1) R = read, W = write 2) xx = reserved bit, read as 0 Figure 1242. TMS320C32 CPU/DMA Interrupt-Enable RegisterNotes: 1) R = read, W = write 2) xx = reserved bit, read as 0 440 Table 127. CPU/DMA Interrupt-Enable Register Bits 441 Table 127. CPU/DMA Interrupt-Enable Register Bits (Continued)443 Table 128.TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules12.3.7 DMA and InterruptsInterrupt Vector Table and Prioritization 12.3.7.1 Interrupts and Synchronization of DMA Channels 444 Figure 1243. Mechanism for No DMA Synchronization445 Figure 1244. Mechanism for DMA Source SynchronizationFigure 1245. Mechanism for DMA Destination Synchronization 446 Figure 1246. Mechanism for DMA Source and Destination Synchronization12.3.8 DMA Memory Transfer Timing12.3.8.1 Single DMA Memory Transfer Timing 447 T448 Figure 1247. DMA Timing When Destination is On Chip449 Figure 1248. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus450 Figure 1248. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued)Write followed by read incurs in one extra half-cycle. 12-72 451 Figure 1249. DMA Timing When Destination is an IOSTRB Bus454 Example 128. Array Initialization With DMA455 Example 129. DMA Transfer With Serial-Port Receive Interrupt456 Example 1210. DMA Transfer With Serial-Port Transmit Interrupt457 Example 1210. DMA Transfer With Serial-Port Transmit Interrupt (Continued) 459 Assembly Language InstructionsChapter 13Optional Assembler Syntax 460 13.1 Instruction Set468 13.2 Instruction Set SummaryTable 138. Instruction Set Summary 475 13.3 Parallel Instruction Set Summary478 13.4 Group Addressing Mode Instruction Encoding13.4.1 486 13.5 Condition Codes and Flags490 13.6 Individual InstructionsSoftware Applications TMS320C3x General- Purpose Applications Users Guide 13.6.1 Symbols and Abbreviations 491 Table 1313. Instruction Symbols492 13.6.2 Optional Assembler Syntaxis equivalent to label assembles to next source line 493 is not legal.orIndividual Instructions Use the syntax in Table 1314 to designate CPU registers in operands. Note the alternate notation R , 0 27, which is used to designate any CPU register. 494 Table 1314. CPU Register Syntax499 ABSF501 ABSF||STF503 ABSI505 ABSI||STI506 ADDC508 ADDC3Add Integer With Carry, 3-Operand See Section 8.5.2, Example 1 ADDC3 *AR5++(IR0),R5,R2 or ADDC3 R5,*AR5++(IR0),R2 Example 2 ADDC3 R2, R7, R0 510 ADDFAdd Floating-Point Values Example ADDF *AR4++(IR1),R5 512 ADDF3Add Floating Point, 3-Operand See Section 8.5.2, Example 1 ADDF3 R6,R5,R1 ADDF3 R5,R6,R1 Example 2 ADDF3 *+AR1(1),*AR7++(IR0),R4 514 ADDF3||STF515 ADDI516 ADDI3517 ADDl313-59 Assembly Language Instructions Example 1 ADDI3 R4,R7,R5 See Section 8.5.2, Example 2 ADDI3 *AR3(1),*AR6(IR0),R2 518 ADDI3||STI519 ADDl3||STI520 AND522 AND3Bitwise-Logical AND, 3-Operand See Section 8.5.2, Example 1 AND3 *AR0(IR0),*+AR1,R4 Example 2 AND3 *AR5,R7,R4 524 AND3||STI526 ANDNBitwise-Logical AND With Complement Example ANDN @980Ch,R2 528 ANDN3Bitwise-Logical ANDN, 3-Operand See Section 8.5.2, Example 1 ANDN3 R5,R3,R7 Example 2 ANDN3 R1,*AR5++(IR0),R0 530 ASH538 Bcond540 BcondD541 BR542 BRD543 CALL544 CALLcond Call Subroutine Conditionally 545 CALLcond13-87 Assembly Language Instructions Example CALLNZ R5 546 CMPF Compare Floating-Point Value 547 CMPF13-89 Assembly Language Instructions Example CMPF *+AR4,R6 549 CMPF3550 CMPI src, dst dst src dst src dst src 552 CMPI3554 DBcond556 DBcondD558 FIXFloating-Point-to-Integer Conversion Example FIX R1,R2 560 FIX||STI562 FLOATInteger-to-Floating-Point Conversion Example FLOAT *++AR2(2),R5 564 FLOAT||STF566 IACKInterrupt Acknowledge Example IACK *AR5 567 IDLE569 IDLE2570 LDE Load Floating-Point Exponent 571 LDE13-113 Assembly Language Instructions Example LDE R0,R5 572 LDF574 LDFcondLoad Floating-Point Value Conditionally Example LDFZ R3,R5 576 LDFILoad Floating-Point Value, Interlocked Example LDFI *+AR2,R7 578 LDF||LDF580 LDF||STF582 LDILoad Integer Example LDI *AR1(IR0),R5 584 LDIcond586 LDIILoad Integer, Interlocked Example LDII @985Fh,R3 588 LDI||LDI590 LDI||STI591 LDM592 LDP593 LOPOWER595 LSH603 MAXSPEED604 MPYF606 MPYF3Multiply Floating-Point Value, 3-Operand See Section 8.5.2, Example 1 MPYF3 R0,R7,R1 Example 2 MPYF3 *+AR2(IR0),R7,R2 MPYF3 R7,*+AR2(IR0),R2 612 MPYF3||STF618 MPYIMultiply Integer Example MPYI R1,R5 620 MPYI3Multiply Integer, 3-Operand See Section 8.5.2, Example 1 MPYI3 *AR4,*AR1(1),R2 Example 2 MPYI3 *AR4(IR0),R2,R7 623 srcA srcDsrc1 src4 Note: Cycle Count 624 MPYl3||ADDl3626 MPYI3||STI629 srcA srcB srcD srcCsrc4, src1 + src2 Note: Cycle Count srcA srcD src1, src4 + src2 src2, src3 + src4 src1, src2 + src4 src1src4 631 NEGB632 NEGF Negate Floating-Point Value 633 NEGF13-175 Assembly Language Instructions Example NEGF *++AR3(2),R1 635 NEGF||STF636 NEGI638 NEGI||STI639 NOP640 NORM641 NORM13-183 Assembly Language Instructions Example NORM R1,R2 642 NOT Bitwise-Logical Complement 643 NOT13-185 Assembly Language Instructions Example NOT @982Ch,R4 645 NOT||STI646 OR647 OR13-189 Assembly Language Instructions Example OR *++AR1(IR1),R2 649 OR3651 OR3||STI652 POP653 POPF654 PUSH655 PUSHF656 RETIcond Return From Interrupt Conditionally 657 RETIcond13-199 Assembly Language Instructions Example RETINZ 658 RETScond Return From Subroutine Conditionally 659 RETScond13-201 Assembly Language Instructions Example RETSGE 661 RND662 ROL664 ROLC665 ROR666 RORC668 RPTB670 RPTS671 SIGI672 STF673 STFI676 STF||STF677 STI678 STII680 STI||STI681 SUBB683 SUBB3684 SUBC Subtract Integer Conditionally 685 SUBC13-227 Assembly Language Instructions Example 1 SUBC @98C5h,R1 Example 2 SUBC 3000,R0 (3000 = 0BB8h) 686 SUBF Subtract Floating-Point Value 687 SUBF13-229 Assembly Language Instructions Example SUBF *AR0(IR0),R5 688 SUBF3 Subtract Floating-Point Value, 3-Operand 689 SUBF313-231 Assembly Language Instructions Example 1 SUBF3 *AR0(IR0),*AR1,R4 See subsection 8.5.2, Example 2 SUBF3 R7,R0,R6 690 SUBF3||STF691 SUBF3||STF13-233 Assembly Language Instructions Example SUBF3 R1,*AR4(IR1),R0 || STF R7,*+AR5(IR0) See subsection 8.5.2, 692 SUBI694 SUBI3Subtract Integer, 3-Operand See subsection 8.5.2, Example 1 SUBI3 R7,R2,R0 Example 2 SUBI3 *AR2(1),R4,R3 696 SUBI3||STIParallel SUBI3 and STI See subsection 8.5.2, Example SUBI3 R7,*+AR2(IR0),R1 || STI R3,*++AR7 697 SUBRB698 SUBRF699 SUBRI700 SWI702 TRAPcondTrap Conditionally Example TRAPZ 16 704 TSTBTest Bit Fields Example TSTB *AR4(1),R5 706 TSTB3Test Bit Fields, 3-Operand See subsection 8.5.2, Example 1 TSTB3 *AR5(IR0),*+AR0(1) Example 2 TSTB3 R4,*AR6(IR0) 707 XOR708 XOR3 Bitwise-Exclusive OR, 3-Operand 709 XOR313-251 Assembly Language Instructions Example 1 XOR3 *AR3++(IR0),R7,R4 See subsection 8.5.2, Example 2 XOR3 R5,*AR1(1),R1 711 XOR3||STI 712 Instruction Opcodes734 GlossaryAuxiliary-register arithmetic unit. Arithmetic logic unit. AAuxiliary-register arithmetic unit. B 735 CSee also LD0LD31 Central processing unit Dprogram address generation logic. 736 EFFirst-in, first-out buffer. H 737 IInterrupt acknowledge signal Least significant bit. interrupt-trap table pointer Interrupt service routine L 738 MCPU cycle Nonmaskable interrupt Most significant bit. Millions of floating point operations per second MP/MC pin. N 739 OPSee read/write pin Program counte R 740 ST 741 WXSee also A0A23 See also D0D31 Z 742 IndexA 744 B745 C746 D747 E748 FG 749 HIalgorithm 4-21 TMS320C32 2-16 750 L751 M752 NO Pdefinition D-6 memory-mapped registers peripherals on register diagram 2-22 serial ports 2-23 timers 2-23 754 QR 755 S756 T expansion bus I/O cycles 9-219-36 primary bus cycles 9-159-20 compared 1-5 757 UV W X Z
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