Series Connection (AND)
I1 | I2 | I3 | Q1 |
| Q2 |
|
|
|
|
|
|
0 | 0 | 0 | 0 |
| 1 |
|
|
|
|
|
|
1 | 0 | 0 | 0 |
| 0 |
|
|
|
|
|
|
0 | 1 | 0 | 0 |
| 0 |
|
|
|
|
|
|
1 | 1 | 0 | 0 |
| 0 |
|
|
|
|
|
|
0 | 0 | 1 | 0 |
| 0 |
|
|
|
|
|
|
1 | 0 | 1 | 0 |
| 0 |
|
|
|
|
|
|
0 | 1 | 1 | 0 |
| 0 |
|
|
|
|
|
|
1 | 1 | 1 | 1 |
| 0 |
|
|
|
|
|
|
Parallel Connection (OR) |
|
I1 | I2 | I3 | Q1 | Q2 |
|
|
|
|
|
0 | 0 | 0 | 0 | 1 |
|
|
|
|
|
1 | 0 | 0 | 1 | 1 |
|
|
|
|
|
0 | 1 | 0 | 1 | 1 |
|
|
|
|
|
1 | 1 | 0 | 1 | 1 |
|
|
|
|
|
0 | 0 | 1 | 1 | 1 |
|
|
|
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1 | 0 | 1 | 1 | 1 |
|
|
|
|
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0 | 1 | 1 | 1 | 1 |
|
|
|
|
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1 | 1 | 1 | 1 | 0 |
|
|
|
|
|
Exclusive OR Circuit (XOR) |
I1 | I2 | Q1 |
|
|
|
0 | 0 | 0 |
|
|
|
1 | 0 | 1 |
|
|
|
0 | 1 | 1 |
|
|
|
1 | 1 | 0 |
|
|
|
I2
I3
I2
I3
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