DLL Timing Control Registers, RCOMP settings
Post Code | Description |
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0x27 | Enable DRAM Channel I/O Buffers |
0x28 | Enable all clocks on populated rows |
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0x29 | Perform JEDEC memory initialization for all memory rows |
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0x30 | Perform steps required after memory init |
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0x31 | Program DRAM throttling and throttling event registers |
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0x32 | Setup DRAM control register for normal operation and enable |
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0x33 | Enable RCOMP |
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0x34 | Clear DRAM initialization bit in the SB |
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0x35 | Initialization Sequence Completed, program graphic clocks |
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0x43 | Program Thermal Throttling |
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171 | Chapter 4 |
