Major Chips Description 2-71
Table 2-13 PCI1131 Pin Descriptions (Continued)
TERMINAL
Name Slot
Slot
I/O
TYPE
FUNCTION
A+ B≠≠
CardBus PC Card Interface Control Signals (Slots A and B)
CBLOCK 107 42 I/O CardBus Lock. This is an optional signal used to lock a particular
address, ensuring a bus initiator exclusive access. NOTE: This signal is
not supported on the PCI 1131.
CDEVSEL 111 47 I/O CardBus Device Select. When actively driven, this signal indicates that
the PCI 1131 has decoded its address as the target of the current
access. As an input, CDEVSEL indicates whether any device
on the bus has been selected.
CDEVSEL 109 45 I/O CardBus Stop. This signal indicates the current target is requesting the
initiator to stop the current transaction.
CSTSCHG 138 72 ICardBus Status Change. CSTSCHG is used to alert the system to a
change in the READY, WP, or BVD condition of the l/O CardBus PC
Card.
CAUDIO 137
71 ICardBus Audio. This signal is an optional digital input signal from a PC
Card to the system's speaker. CardBus cards support two types of audio:
single amplitude, binary waveform, and/or Pulse Width Modulation
(PWM) encoded signal. The PCI1131 supports the Binary Audio Mode,
and may output a binary audio signal from the PC Card to the
SPKROUT signal.
CIRDY 115 50 I/O CardBus Initiator Ready. This signal indicates that the PCI1131 is
initiating the bus initiator ability to complete a current data phase of the
transaction. It is used in conjunction with CTRDY. When both of these
signals are sampled asserted, a data phase is completed on any clock.
During a write, CIRDY indicates that valid data is present on CAD31-0,
and during a read, it indicates the PCI 1131, as an initiator, is prepared
to accept the data. Wait cycles are inserted until both CTRDY and
CFRDY are both low (asserted).
CTRDY 114 49 I/O CardBusTargetReady. This signal indicates that the PCI 1131, as a
selected targets has the ability to complete a current data phase of the
transaction. It is used in conjunction with CIRDY. When both of these
signals are sampled asserted, a data phase is completed on any clock.
During a read, CTRDY indicates that valid data is present on CAD31-0,
and during a write, it indicates the PCI 1131, as a target, is prepared to
accept the data. Wait cycles are inserted until both CIRDY and CTRDY
are both low (asserted).
CFRAME 116 51 I/O CardBus Cycle Frame. This signal is driven by the PCI 1131 when it is
acting as an initiator to indicate the beginning and duration of a
transaction. CFRAME is asserted to indicated a bus transaction is
beginning, and while it is asserted, data transfer is continuous. When
CFRAME is high (deasserted), the transaction is in its final data phase.
+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25.
≠ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.