Acer 61X - page 129

2-72 Service Guide

Table 2-13 PCI1131 Pin Descriptions (Continued)

TERMINAL

Name Slot

Slot

I/O

TYPE

FUNCTION

A+ B≠≠

CardBus PC Card Interface Control Signals (Slots A and B)

CREQ 127 61 ICardBus Request. This signal ir1dicates to the arbiter that the CardBus

PC Card desires use the CardBus bus.

CGNT 110 46 OCardBus Grant. This signal is driven by the PCI 1131 to grant a CardBus

PC Card access to the CardBus bus after the current data transaction

has completed

CPERR 108 43 I/O CardBus Parity Error. This signal reports errors during all CardBus PC

Card transactions except during special cycles. This signal is sustained

in a high-impedance state and must be driven active by the agent

receiving data, two clocks following the data, when a data parity error is

detected. This signal must be driven active for a minimum duration is

one clock for each data phase. CPERR must be driven high for one clock

before it is returned to the high-impedance state. An agent cannot report

a CPERR until it has claimed the access by asserting CDSVSEL and

completed a data phase.

CSERR 136 70 ICardBus System Error. This signal reports address parity error, data

errors on the Special Cycle command, or any other system error where

the result could be catastrophic, such that the CardBus card may no

longer operate correctly. CSERR is open drain and is actively driven for

a single CardBus PC Card clock by the agent reporting the error. The

assertion of this signal is synchronous to the Cock and meets the setup

and hold times of all bussed signals. Restoring of the CSERR to the

deasserted states is accomplished by a weak pull-up which is provided

by the system designer. This pull-up may take two to three clock periods

to fully restore ~R The PCI1131 reports CSERR to the operating system

anytime it is sampled low (asserted)

CVS1 134 68

CVS2 122 56

I/O CardBus Voltage Sense 1 and Voltage Sense 2. CVS1 and CVS2, are

used in conjunction with each other, along with CCD1 and CCD2, to

determine the operating voltage of the CardBus PC Card.

CINT 135 69 ICardBus Interrupt. This signal is asserted low by a CardBus PC Card to

request interrupt servicing from the host.

+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25.

≠ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.

Contents

Main Copyright Disclaimer Purpose Manual Structure Page Conventions Page Table of Contents Chapter 1 System Introduction Chapter 2 Major Chips Description Page Chapter 3 BIOS Setup Information Chapter 4 Disassembly and Unit Replacement Page List of Figures Page Page List of Tables Page Page Page Page 1.1.2 Rear Ports 1.1.3 Indicator Light Page System Introduction 1-5 1.1.4 System Specifications Overview Table 1-3 System Specifications Item Standard Optional 1-6Service Guide Table 1-3 System Specifications (continued) Item Standard Optional Page Page Page Page Page 1.3 Jumpers and Connectors Page 1-14 Service Guide 1.4 Hardware Configuration and Specification 1.4.1 Memory Address Map Table 1-7 Memory Address Map Address Range Definition Function 1.4.2 Interrupt Channel Map Table 1-8 Interrupt Channel Map Priority Interrupt Number Interrupt Source 1.4.4 I/O Address Map Table 1-10 I/O Address Map Address Range Device 1-16 Service Guide 1.4.5 M7101 GPIO (General Purpose I/O) Port Definition Table 1-13 BIOS Specifications Table 1-11 M7101 GPIO Port Definition Item Description 1.4.6 Processor Table 1-12 Processor Specifications Page 1.4.9 Second-Level Cache 1.4.10 Video Memory 1.4.11 Video Page 1.4.12 Parallel Port 1.4.13 Serial Port 1.4.14 Audio 1.4.15 PCMCIA 1.4.16 Touchpad 1.4.17 Keyboard 1-24 Service Guide 1.4.18 FDD Table 1-26 FDD Specifications 1.4.19 HDD Table 1-27 HDD Specifications System Introduction 1-25 1.4.20 CD-ROM Table 1-28 CD-ROM Specifications 1.4.21 Battery Table 1-29 Battery Specifications 1.4.22 Charger 1.4.23 DC-DC Converter 1.4.24 DC-AC Inverter 1-28 Service Guide 1.4.25 LCD Table 1-33 LCD Specifications System Introduction 1-29 1.4.26 AC Adapter Table 1-34 AC Adapter Specifications 1.5 Software Configuration and Specification 1.5.1 BIOS Page Page 1.5.2 Drivers, Applications and Utilities Page 1-38 Service Guide 1.7 Environmental Requirements Table 1-42 Environmental Requirements 1.8 Mechanical Specifications C h a p t e r 2C h a p t e r 2 Major Chips Description 2.1 Major Component List 2.2 ALI M1521 2.2.1 Features Supports all Intel/Cyrix/AMD 586-class processors (with host bus of 66 MHz, 60 MHz and Supports asynchronous/pipeline-burst SRAM Supports FPM/EDO/BEDO/SDRAM DRAMs Page 2.2.2 Block Diagram 2.2.3 System Architecture ALADDIN-III SYSTEM ARCHITECTURE M1521 M1523 GC DRAM 586 CPU 2.2.4 Data Path Figure 2-3 M1521 Data Path E C C M1521 Page 2-8Service Guide 2.2.6 Signal Descriptions Table 2-2 M1521 Signal Descriptions Major Chips Description 2-9 2-10 Service Guide Major Chips Description 2-11 2-12 Service Guide Major Chips Description 2-13 2.3 ALI M1523 2.3.1 Features Technology Provides a bridge between the PCI bus and ISA bus Buffers Page 2-16 Service Guide 2.3.2 Block Diagram Figure 2-5 M1523 Block Diagram M1523 Block Diagram Major Chips Description 2-17 2.3.3 Pin Diagram Figure 2-6 M1523 Pin Diagram ALi M1523 2-18 Service Guide 2.3.4 Signal Descriptions Table 2-3 M1523 Signal Descriptions Major Chips Description 2-19 2-20 Service Guide Major Chips Description 2-21 2-22 Service Guide Major Chips Description 2-23 Page Major Chips Description 2-25 2.4.2 Pin Diagram Figure 2-7 M7101 Pin Diagram ALi M7101 2-26 Service Guide 2.4.3 Pin Description Table 2-4 M7101 Pin Descriptions Major Chips Description 2-27 2-28 Service Guide Major Chips Description 2-29 2-30 Service Guide Major Chips Description 2-31 2-32 Service Guide Major Chips Description 2-33 2.4.4 Different Pin definition setting SLED, CCFT, DISPLAY, SPKCTL, SQWO and GPIOC2 pins are all internal pull high 50K Pull high : GPIOA0, GPIOA4, GPIOB1, GPIOB3, GPIOB6, GPIOB7, GPIOC1, GPIOC2, Pull low : Other GPIO pins. 2-36 Service Guide 2.4.5 Numerical Pin List Table 2-7 M7101 Numerical Pin List No. Pin Name Type No. Pin Name Type Major Chips Description 2-37 2.4.6 Alphabetical Pin List Table 2-8 M7101 Alphabetical Pin List No. Pin Name Type No. Pin Name Type 2.4.7 Function Description Major Chips Description 2-39 Table 2-9 M7101 PCI Interface Lock Register Action I/O Port 0178h/0078h I/O Port 017Ah/007Ah Figure 2-8 State Machine for PCI Interface State Machine for PCI Interface. 2.5 C&T 65550 High Performance Flat Panel/CRT VGA Controller 2.5.1 Features Page Page Major Chips Description 2-43 2.5.4 Pin Descriptions Table 2-10 C&T 65550 Pin Descriptions 2-44 Service Guide Major Chips Description 2-45 2-46 Service Guide Major Chips Description 2-47 2-48 Service Guide Major Chips Description 2-49 2-50 Service Guide Major Chips Description 2-51 2-52 Service Guide Major Chips Description 2-53 2-54 Service Guide Table 2-11 Flat Panel Display Interface Configurations Page 2.6 TI PCI1131 CardBus Controller 2.6.1 Overview Page Page Page Page Page Page Major Chips Description 2-63 2.6.6 Terminal Functions NAME NO. Table 2-13 PCI1131 Pin Descriptions 2-64 Service Guide NAME NO. Page 2-66 Service Guide A+ B Major Chips Description 2-67 A+ B 2-68 Service Guide A+ B Major Chips Description 2-69 A+ B 2-70 Service Guide A+ B Major Chips Description 2-71 A+ B Page Major Chips Description 2-73 TERMINAL NAME NO I /O TYPE FUNCTION 2-74 Service Guide Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL NAME NO I /O TYPE FUNCTION 2.7 NS87336VJG Super I/O Controller 2.7.1 Features 100% compatible with ISA, and EISA architectures The Floppy Disk Controller: The Bidirectional Parallel Port: The UARTs: The Address Decoder Enhanced Power Management Mixed Voltage support Plug and Play Compatible: Figure 2-15 NS87336VJG Block Diagram 100-Pin TQFP package - PC87336VJG 2.7.2 Block Diagram Page Major Chips Description 2-79 2.7.4 Pin Description Table 2-14 NS87336VJG Pin Descriptions 2-80 Service Guide Major Chips Description 2-81 2-82 Service Guide Major Chips Description 2-83 2-84 Service Guide Major Chips Description 2-85 2-86 Service Guide Page Page Major Chips Description 2-89 2.8.3 Pin Descriptions Table 2-15 YMF715 Descriptions Pin name Pins I/O Type Size Function 2-90 Service Guide Table 2-15 YMF715 Descriptions (Continued) Pin name Pins I/O Type Size Function Multi-purpose Dins: 13 pins Page Providing low battery warning signals when the system using battery as the main power 2.9.3 Absolute Maximum Ratings 2.9.4 Electrical Characteristics Major Chips Description 2-93 2.9.5 Pin Diagram Major Chips Description 2-95 2.9.6 Pin Description Table 2-18 T62.062.C Pin Description table Item Pin Name I/O Description 2.9.7 Functions Description Page 2.10 T62.061.C DC-DC Converter 2.10.1 Pin Diagram 2.10.2 Pin Assignment Page +2.35V:(2.45V) Load : 0A-4.2A Regulation: +5%, -4% +12V : Load : 0A-0.15A Regulation: +/-5% +6V : Load : 0A~0.1A Regulation: 5.5V~7.5V 5VSB:Load : 5mA Regulation:+/-10% 2.10.4 Control Page 2.11 T62.064.C DC-AC Inverter (11.3") 2.11.1 Electrical Specifications 2.11.2 Pin & Connector Assignment Page 2.12 T62.066.C DC-AC Inverter (12.1") 2.12.1 Electrical Specifications 2.12.2 Pin & Connector Assignment Page C h a p t e r 3C h a p t e r 3 BIOS Setup Information Page Page 3.3 Basic System Configuration 3.3.1 Date and Time 3.3.2 Floppy Disk Drives 3.3.3 Hard Disk Drive 3.3.4 Large Hard Disk Capacity 3.3.5 Memory Test [Disabled] 3.3.6 Boot Display 3.3.7 Quiet Boot 3.4 System Security 3.4.1 Floppy Disk Drive Control 3.4.2 Hard Disk Drive Control 3.4.3 System Boot Drive Control 3.4.4 CD-ROM Bootable Page Capabilities Port(ECP)] . The default value, with ECP selected, is [0] 3.4.8 Passwords 3.4.9 CardBus Support 3.5 Power Management Settings 3.5.1 Power Management Mode [Disabled] to turn off all the timers. The default setting is [Enabled] 3.5.2 Display Standby Timer 3.5.3 Hard Disk Standby Timer 3.5.4 System Sleep Timer 3.5.5 System Sleep Mode 3.5.6 System Resume Timer Mode 3.5.7 System Resume Date and Time 3.5.8 Modem Ring Resume On Indicator Page 3.6 System Information Reference Page 3.7 Load Setup Default Settings C hC h a p t a p t e r 4 e r 4 Disassembly and Unit Replacement 4.1 General Information 4.1.1 Before You Begin 4.1.2 Connector Types Connectors with no locks Connectors with locks Unplugging the Cable Plugging the Cable 4.1.3 Disassembly Sequence Page 4.2 Replacing Memory 4.3 Removing the Hard Disk Drive Page Page Page Page 4.5.3 Replacing the CPU Page Page Page Page Page Page Page Page Page 4.6 Disassembling the Display Page Page Page A p A p p e n d p e n d i x Ai x A Model Number Definition Model Number Definition A-1 Memory and Battery Page Page Page Page A p A p p e n d p e n d i x Ci x C Spare Parts Spare Parts C-1 This appendix lists the spare parts of the notebook TI EXTENSA 610. Table C-1 Spare Parts List C-2Service Guide Table C1 Spare parts list (continued) Spare Parts C-3 Table C1 Spare parts list (continued) Page Page Page Page P55C/P54C CPU BUS & CACHE PCI & DRAM PCI-ISA BRIDGE & IDE M1523 Page Page ## REMOVE R65,R178,R182,R181,R66 PAD Page ## REMOVE U53 PAD TRACKSTICK CONN KB BD CONN. Page ## CIRCUIT MODIFY Page Page Page Page Page Page Page Page Page Page Page ALADDIN III COMMON POWER: VCC_IDE & GND CPU BYPASS CAPACITORS CACHE M1523 A p A p p e n d p e n d i x Ei x E BIOS POST Checkpoints BIOS POST Checkpoints E-1 This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List E-2Service Guide Table E-1 POST Checkpoint List (Continued) BIOS POST Checkpoints E-3 Table E-1 POST Checkpoint List (Continued) Checkpoint Description