2-86 Service Guide
Table 2-14 NS87336VJG Pin Descriptions (continued)
Pin No. I/O Description
TC 4ITerminal Count. Control signal from the DMA controller to indicate
the termination of a DMA transfer. TC is accepted only when FDACK
is active. TC is active high in PC-AT and Model 30 modes, and
active low in PS/2 mode.
/TRK0
(Normal Mode) 35 IFDC Track 0. This input indicates the controller that the head of the
selected floppy disk drive is at track zero.
/TRK0
(PPM Mode) 91 IFDC Track 0. This pin gives an additional Track 0 signal in PPM
Mode when PNF = 0.
VDDB, C 48, 97 Power Supply. This is the 3.3V/5V supply voltage for the
PC87332VJG circuitry.
VSSB-E 40, 7,
88, 59 Ground. This is the ground for the PC87332VJG circuitry.
/WAIT 82 IEPP Wait. This signal is used in EPP mode by the parallel port
device to extend its access cycle. It is an active low signal.
/WDATA
(Normal Mode) 37 OFDC Write Data. This output is the write precompensated serial data
that is written to the selected floppy disk drive. Precompensation is
software selectable.
/WDATA
(PPM Mode) 81 OFDC Write Data. This pin provides an additional Write Data signal in
PPM Mode when PNF=0. (See PE.)
/WGATE
(Normal Mode) 36 OFDC Write Gate. This output signal enables the write circuitry of the
selected disk drive. WGATE has been designated to prevent glitches
during power-up and power-down. This prevents writing to the disk
when power is cycled.
/WGATE
(PPM Mode) 80 OFDC Write Gate. This pin gives an additional Write Gate signal in
PPM mode when PNF = 0.
/WP
(Normal Mode) 34 IFDC Write Protect. This input indicates that the disk in the selected
drive is write protected.
/WP
(PPM Mode) 90 IFDC Write Protect. This pin gives an additional Write Gate signal in
PPM mode when PNF = 0.
/WR 16 IWrite. An active low input to signal a write from the microprocessor
to the controller.
/WRITE 93 OEPP Write Strobe. This signal is used in EPP mode as write strobe.
It is active low.
X1/OSC 5ICrystal1/Clock. One side of an external 24 MHz/48 MHz crystal is
attached here. If a crystal is not used, a TTL or CMOS compatible
clock is connected to this pin.
X2 6OCrystal 2. One side of an external 24 MHz/48 MHz crystal is attached
here. This pin is left unconnected if an external clock is used.
/ZWS 1OZero Wait State. This pin is the Zero Wait State open drain output
pin when bit 6 of FCR is 0. ZWS is driven low when the EPP or ECP
is written, and the access can be shortened.