Advantech PCI-1710 4.1 Overview, 4.2 I/O Port Address Map

28 PCI-1710/1710HG User's Manual

4.1 Overview

The PCI-1710/1710HG is delivered with an easy-to-use 32-bit DLL

driver for user programming under the Windows 95/NT operating

system. We advise users to program the PCI-1710/1710HG using the

32-bit DLL driver provided by Advantech to avoid the complexity of

low-level programming by register.

The most important consideration in programming the PCI-1710/

1710HG card at a register level is to understand the function of the

card’s registers. The information in the following sections is provided

only for users who would like to do their own low-level programming.

4.2 I/O Port Address Map

The PCI-1710/1710HG card requires 32 consecutive addresses in the

PC’s I/O space. The address of each register is specified as an offset

from the card’s base address. For example, BASE+0 is the card’s base

address and BASE+7 is the base address plus seven bytes.

Table 4-1 shows the function of each register or driver and its address

relative to the card’s base address.

Contents

Main Page Contents Chapter 5: Calibration............................................ 4 5 Appendix A: 82C54 Counter Chip Functions ...... 5 1 Page 1.1 Introduction PCI-bus Plug and Play Flexible Inputs Types and Ranges Setting On-board FIFO (First In First Out) Memory On-board Programmable Counter 1.2 Features 1.3 Specifications Analog Input: Page Analog Output: Digital Input: Digital Output: Programmable Timer/Counter General: 8PCI-1710 /1710HG User's Manual 1.4 Block Diagram Figure 1-1: PCI-1710/PCI-1710HG block diagram Page 2.1 Initial Inspection 2.2 Unpacking 2.3 Installation Instructions Page Page 3.1 Overview 3.2 I/O Connector Pin Assignment Figure 3-1: I/O connector pin assignments for the PCI-1710/1710 HG card Chapter 3 Signal Connections 15 16 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions Chapter 3 Signal Connections 17 I/O Connector Signal Descriptions (part II) 18 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions (part III) 3.3 Analog Input Connections Single-ended Channel Connections Differential Channel Connections ExternalInternal Page Page 3.4 Analog Output Connections 3.5 Trigger Source Connections Internal Pacer Trigger Connection External Trigger Source Connection 3.6 Field Wiring Considerations Page Page 4.1 Overview 4.2 I/O Port Address Map Chapter 4 Register Structure and Format 29 Table 4-1: PCI-1710/1710HG register format (Part 1) Table 4-1: PCI-1710/1710HG register format (Part 2) 30 PCI-1710/1710HG User's Manual Table 4-1: PCI-1710/1710HG register format (Part 3) Chapter 4 Register Structure and Format 31 Table 4-1: PCI-1710/1710HG register format (Part 4) 32 PCI-1710/1710HG User's Manual 4.3 Channel Number and A/D Data BASE+0 and BASE+1 4.4 Software A/D Trigger BASE+0 4.5 A/D Channel Range Setting BASE+2 PCI-1710 The following table lists the gain codes for the PCI-1710: PCI-1710HG 4.6 MUX ControlBASE+4 and BASE+5 Page 4.7 Control Register BASE+6 4.8 Status Register BASE+6 and BASE+7 4.9 Clear Interrupt and FIFO BASE+8 and BASE+9 Page 4.12 D/A Reference Control BASE+14 Page Page 5.1 Introduction 5.2 VR Assignment 5.3 A/D Calibration 5.4 D/A Calibration 5.5 Self A/D Calibration Page Page A.1 The Intel 82C54 Counter 0 Counter 1 & 2 A.2 Counter Read/Write and Control Registers Description: Page Page A.3 Counter Operating Modes MODE 0 Stop on Terminal Count MODE 1 Programmable One-shot Pulse MODE 2 Rate Generator MODE 3 Square Wave Generator MODE 4 Software-Triggered Strobe MODE 5 Hardware-Triggered Strobe A.4 Counter Operations Read/Write Operation Counter Read-back Command Counter Latch Operation