Advantech PCI-1710 4.12 D/A Reference Control BASE+14

Chapter 4 Register Structure and Format 43

4.12 D/A Reference Control BASE+14

The write-only register of BASE+14 allows users to set the D/A

reference source.

Table 4-12: Registers for D/A reference control

DA0_5/10 The internal reference voltage for the D/A output

channel 0

This bit controls the internal reference voltage for the D/A output

channel 0. 0 means that the internal reference voltage is 5 V, and 1

means it is 10 V.

DA0_I/E Internal or external reference voltage for the D/A output

channel 0

This bit indicates that the reference voltage for the D/A output channel

0 is internal or external. 0 means that the reference voltage comes

from the internal source, and 1 means it comes from an external

source.

DA1_5/10 The internal reference voltage for the D/A output

channel 1

This bit controls the internal reference voltage for the D/A output

channel 1. 0 means that the internal reference voltage is 5 V, and 1

means it is 10 V.

DA1_I/E Internal or external reference voltage for the D/A output

channel 1

This bit indicates that the reference voltage for the D/A output channel

1 is internal or external. 0 means that the reference voltage comes

from the internal source, and 1 means it comes from an external

source.

Write D/A Reference Control

Bit # 7 6 5 4 3 2 1 0

BASE+14 DA1_I/E DA1_5/10 DA0_I/E DA0_5/10

Contents

Main Page Contents Chapter 5: Calibration............................................ 4 5 Appendix A: 82C54 Counter Chip Functions ...... 5 1 Page 1.1 Introduction PCI-bus Plug and Play Flexible Inputs Types and Ranges Setting On-board FIFO (First In First Out) Memory On-board Programmable Counter 1.2 Features 1.3 Specifications Analog Input: Page Analog Output: Digital Input: Digital Output: Programmable Timer/Counter General: 8PCI-1710 /1710HG User's Manual 1.4 Block Diagram Figure 1-1: PCI-1710/PCI-1710HG block diagram Page 2.1 Initial Inspection 2.2 Unpacking 2.3 Installation Instructions Page Page 3.1 Overview 3.2 I/O Connector Pin Assignment Figure 3-1: I/O connector pin assignments for the PCI-1710/1710 HG card Chapter 3 Signal Connections 15 16 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions Chapter 3 Signal Connections 17 I/O Connector Signal Descriptions (part II) 18 PCI-1710/1710HG User's Manual I/O Connector Signal Descriptions (part III) 3.3 Analog Input Connections Single-ended Channel Connections Differential Channel Connections ExternalInternal Page Page 3.4 Analog Output Connections 3.5 Trigger Source Connections Internal Pacer Trigger Connection External Trigger Source Connection 3.6 Field Wiring Considerations Page Page 4.1 Overview 4.2 I/O Port Address Map Chapter 4 Register Structure and Format 29 Table 4-1: PCI-1710/1710HG register format (Part 1) Table 4-1: PCI-1710/1710HG register format (Part 2) 30 PCI-1710/1710HG User's Manual Table 4-1: PCI-1710/1710HG register format (Part 3) Chapter 4 Register Structure and Format 31 Table 4-1: PCI-1710/1710HG register format (Part 4) 32 PCI-1710/1710HG User's Manual 4.3 Channel Number and A/D Data BASE+0 and BASE+1 4.4 Software A/D Trigger BASE+0 4.5 A/D Channel Range Setting BASE+2 PCI-1710 The following table lists the gain codes for the PCI-1710: PCI-1710HG 4.6 MUX ControlBASE+4 and BASE+5 Page 4.7 Control Register BASE+6 4.8 Status Register BASE+6 and BASE+7 4.9 Clear Interrupt and FIFO BASE+8 and BASE+9 Page 4.12 D/A Reference Control BASE+14 Page Page 5.1 Introduction 5.2 VR Assignment 5.3 A/D Calibration 5.4 D/A Calibration 5.5 Self A/D Calibration Page Page A.1 The Intel 82C54 Counter 0 Counter 1 & 2 A.2 Counter Read/Write and Control Registers Description: Page Page A.3 Counter Operating Modes MODE 0 Stop on Terminal Count MODE 1 Programmable One-shot Pulse MODE 2 Rate Generator MODE 3 Square Wave Generator MODE 4 Software-Triggered Strobe MODE 5 Hardware-Triggered Strobe A.4 Counter Operations Read/Write Operation Counter Read-back Command Counter Latch Operation