Table 4-2. Signal-Name Descriptions
Mnemonic | Function |
| Sheet 1 | Sheet 2 | Sheet 3 |
| CONTROL BOARD |
| 4D |
|
|
ACLR* | Analog circuits clear (D) |
|
| 2B | |
BO* | Brown out input disable (D) |
| 3D |
| 2A |
CC_EN* | CC mode enable (D) |
| 6D, 3B |
|
|
CC_PROG | Programming voltage for CC mode (A) |
| 3B | 2B |
|
CCVTST | Comparator output, main DAC | 6D | 4A |
| |
CG* | 5D | 4D |
| ||
CLR | Initialize transient generator (D) |
| 7B, 5A |
|
|
CR* |
| 5D | 3C | 2A | |
CS0* | Main DAC chip select (D) |
| 1D | 8D |
|
CS1* | Transient DAC chip select (D) |
| 1D | 7C |
|
CS2* | Slew range chip select (D) |
| 1D, 8C |
|
|
CS3* | Readback DAC chip select (D) |
| 1D | 8B |
|
CS4* | 1D | 8D |
| ||
CS5* |
| 1D, 6D |
|
| |
CS6* |
| 7D, 5D |
|
| |
CS7* | 8D 3C, 2C |
|
| ||
CV_EN* | CV mode enable (D) |
| 6D, 3C |
|
|
CV_PROG | Programming voltage for CV mode (A) |
| 3C |
| 2C |
DAC_REF* | Main DAC reference enable, CV/CC modes (D) | 5D | 3D |
| |
E |
| 6D, 8A |
| 2D | |
EEPON* | EEPROM |
| 2C |
| |
EPC_EN* | Extended power capability enable/disable (D) | 4D |
| 2A | |
EXT_PROG | Ext programming input (A) from | 3D |
| 1B, 3C | |
FLT | 1B |
| |||
FSEL0,FSEL1,FSEL2 | 5D, 4A |
|
| ||
HIGH* |
| 6B | 8C |
| |
H/L* |
| 7D | 8D |
| |
| 7D | 8B |
| ||
IMON |
| 1D, 1C |
| ||
IMON* |
|
| 3D, 6A | 2C | |
|
| 4C |
| ||
IMONR |
| 6D | 4A |
| |
LCLR* | Clear status latch (D) |
| 5D, 3D |
| 8B |
MODULE_INSTALLED* | Indicate how many modules are installed (D) |
|
| ||
OP* | Overpower status (D) |
| 3D |
| 2A |
OV* | Overvoltage status (D) |
| 3D |
| 2A |
PCLR1* | 3D |
| 8B | ||
PORT | PORT output (D) to |
| 1B |
| |
PRX |
|
|
| 8A | |
PTX |
|
|
| 8A | |
P_TRIG | Continuous mode pulse trigger (D) |
| 6A, 5D |
| 8B |
PRI_TRIG | Trigger signal from mainframe (D) |
| 4D, 6B |
| |
PULSE_EN |
|
|
| ||
RCK_HI* | Loads |
| 1D, 6A |
|
|
RCK_LOW* | Loads |
| 1D, 6A |
|
|
RNG |
| 7C |
| 2B | |
(A) = analog signal | (D) = digital signal | 8C = signal origin |
|
|
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