The CYCLE variable | The CYCLE variable is made up of the following signals: TRDY#, | |||||||
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| FRAME#, IRDY#, C/BE(3:0), DEVSEL# , and STOP#. This variable has | ||||||
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| 27 symbols defined that can be used to help make triggering, timing | ||||||
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| analysis and pattern filtering easier. The following lists the bit pattern | ||||||
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| and the corresponding symbol. |
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| Symbol | C/BE(3:0 | FRAME# | IRDY# | DEVSEL# | TRDY# | STOP# |
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| INTACK | 0000 | 0 | 1 | 1 | 1 | 1 |
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| SPECIAL CYCLE | 0001 | 0 | 1 | 1 | 1 | 1 | |
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| I/O READ | 0010 | 0 | 1 | 1 | 1 | 1 |
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| I/O WRITE | 0011 | 0 | 1 | 1 | 1 | 1 |
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| RESERVED | 0100 | 0 | 1 | 1 | 1 | 1 |
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| RESERVED1 | 0101 | 0 | 1 | 1 | 1 | 1 |
| MEM RD DWORD | 0110 | 0 | 1 | 1 | 1 | 1 | |
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| MEM WRITE | 0111 | 0 | 1 | 1 | 1 | 1 |
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| MEM RD BL | 1000 | 0 | 1 | 1 | 1 | 1 |
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| MEM WR BL | 1001 | 0 | 1 | 1 | 1 | 1 |
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| CONF READ | 1010 | 0 | 1 | 1 | 1 | 1 |
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| CONF WRITE | 1011 | 0 | 1 | 1 | 1 | 1 |
| SPLIT COMPLETION | 1100 | 0 | 1 | 1 | 1 | 1 | |
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| DAC | 1101 | 0 | 1 | 1 | 1 | 1 |
| MEM RD BLOCK | 1110 | 0 | 1 | 1 | 1 | 1 | |
| MEM WR BLOCK | 1111 | 0 | 1 | 1 | 1 | 1 | |
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| IO XACTION | 001X | 0 | 1 | 1 | 1 | 1 |
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| ADDR CYCLE | XXXX | 0 | 1 | 1 | 1 | 1 |
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| DATA XFER | XXXX | X | 0 | 0 | 0 | 1 |
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| IDLE | XXXX | 1 | 1 | X | X | X |
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| RETRY | XXXX | X | 0 | 0 | 1 | 0 |
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| DISC NXT ADB | XXXX | X | 0 | 0 | 0 | 0 |
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| DECODE | XXXX | 0 | 1 | 1 | 1 | 1 |
| SINGLE DATA DISCON | XXXX | 0 | 0 | 1 | 0 | 0 | |
| TARGET ABORT | XXXX | X | 1 | 1 | 1 | 0 | |
| TARGET RESPONSE (WAIT) | XXXX | 0 | 0 | 0 | 1 | 1 | |
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| WAIT | XXXX | 0 | 0 | 1 | 1 | 1 |
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