I INDEX
A
address enable switch (SW1.1),
asynchronous memory bank,
architecture, of
B
bill of materials,
board schematic
C
configuration, of
J2 (PHY devices),
D
dimensions, of
E
Ethernet interface, viii,
software documentation,
F
flag pins, See programmable flags (PFs) flags enable switch (SW1.2),
I
interfaces, See Ethernet, USB, Poe, MII IOS switch
IRQ line,
J
J2 connector,
map of locations,
L
LAN
devices, viii,
link jumper (JP3),
M
Media Access Control (MAC) address,
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