BIOS SPECIFICATION
6-18
6. Devices
6.0 CPU
The CPU supported by S62F system is Intel mobile Yonah dual core processor.
The supported frequency is from 1.66GHz to 2.16GHz.
6.1 NORTH BRIDGE (CALISTOGA)
6.1.1 DRB Registers (dram row boundary registers)
The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM
rows with granularity of 128MB. The offset of these registers are 100h~103h. The following is the
mapping of the registers.
DRB0(row 0) : 100h
DRB1(row 1) : 101h
DRB2(row 2) : 102h
DRB3(row 3) : 103h
DRB0 = Total memory in row 0 (in 128MB increments)
DRB1 = Total memory in row 0 + row 1 (in 128MB increments)
DRB2 = Total memory in row 0 + row 1+ row 2 (in 128MB increments)
DBR3 = Total memory in row 0 + row 1 + row 2 + row 3 (in 128MB increments)
6.2 SOUTH BRIDGE (ICH7 - M)
6.2.1 Hub Interface To PCI Bridge
6.2.1.1 Features
The device allows software to “hide” PCI devices(0~5) in terms of configuration space.
Specifically, when PCI devices(0~5) are hidden, the configuration space is not accessible
because the PCI IDSEL pin does not assert. The ICH7-M supports the hiding of 7 external
devices, which matches the number of PCI request/grant pairs, and the ability to hide the
integrated LAN device by masking out the configuration space decode of LAN controller.
6.2.2 LPC Interface Bridge
6.2.2.1 Specific I/O Base Address (PMBASE, GPIOBASE, TCOBASE)
Two specific I/O Base Addresses are defined in this device – PMBase, GPIOBase . PMBase
is defined in register 0x40~0x43, also called ACPIBase. The registers offset based on
PMBase(ACPIBase) are ACPI2.0 compliance. GPIOBase is defined in register 0x48~0x4B.
OS/Utilities can read/write the related I/O registers based on it to control GPIO function, level
and interrupt type. Following is the registers setting programmed by BIOS.
PMBase Address : 0800h
GPIOBase Address : 0 480h
6.2.2.2 Interrupt
This section contains some interrupts configuration and relative PCI registers.
6.2.2.2.1 SCI Interrupt
SCI IRQ routing is generally set to IRQ9. (Power On Default). The relative register is
PCI register 0x44. IRQ Selections are described below.
Bit2:0 : 000 -> IRQ9