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5.0 TROUBLE ANALYSIS
5.1 BUILT IN TEST AND DIAGN OSTICS
Built in test functions are provided for the VX462B in the form of read back registers. The
VXIbus registers perform as defined in the VXIbus specification and the timing and control
registers have read back capability for data verification and test.
5.2 TROUBLE ANALYSIS GUIDE
The first approach to troubleshooting is to attempt a A16 VXIbus access. A successful access
(read or write) will not produce a bus error. If a bus error occurs, a probable cause is an
improper ly set logical address . Check this s etting and ve rify the progr am for prope r addr essing.
If no bus error occurs, read the first two VXIbus registers. The expected device type is 'FFFD',
and t he expected ID is 'FFC1' (refer to the paragraph 3.5.1 for the Device Type and ID bit
locatio ns).
To check the register write capability, write a value to the Pulse Width Regist er, t hen rea d it ba ck.
The returned value should match the data written with the exception of t he unused bits. If the
module is res ponding as e xpecte d, prog ram a pulse st ream and monit or the Pulse Ou t with an
oscilloscope. If no signal is seen or is not as expected, utilize the modules read back capability to
verify that all registers are correct ly set. When diag nosing o utput problems, isolate the mod ule
from ext ernal loa ds by re moving the connec tor.