CH Tech Pulse Generator

4.2 PROGRAMMING SEQUENCE

The RUN bit in the Pulse Control Register is the basic On/Off control for pulse generation. A

separate out put relay connects/disconnect s the generated pulse to/from the BNC connector . The

output relay is controlled by the OEN bit in the PRI Register. Before enabling the RUN control

bit or o utput re lay, be sure to progr am all of the timing and voltage level registers a s prescribed in

this manual. Special care should be taken to check the registers for timing over runs and output

voltage levels. To prevent damage t o the users cir cuitry, the following st eps should be followed

when programming:

1) Disable the output relay and reset RUN.

2) Program Voltage R eferences .

3) Setup Timing registers and control functions.

4) Enable the output relay.

5) Enable RUN.

4.3 NORMAL MODES OF OPERATION

The three normal modes of operation are single pulse, delayed pulse, and double pulse. All three

modes of op eration and their relationship to trigger out are described below. The Trigger Output

signal indicates the beginning of a pu lse cycle. It occurs 50-75ns after the RUN bit is set or the

trigger input signal goes high. The width of trigger out is equal to the pulse width range selected

(i.e., 25ns, 100ns, 1s, etc.).

4.3.1 Single Pulse Mode

Single pulse mode produces the desired pulse immediately (approximately 25ns) after trigger out

and is selected when neither delayed or double pulse are selected.

4.3.2 Delayed Pulse Mode

When delayed pulse mode is selec ted, the pulse o ccurs the progr ammed d elay t ime a fter the

trigger out (plus Approximately 25ns). To prevent a pulse overrun, ensure that the delay time and

the pulse width do not extend into the next cycle. The pulse generation logic takes about 75 nsec

to start; therefore, ensure that the delay time + the pulse width is less than the pulse repetition

interval  75 nsec.

4.3.3 Double Pulse Mode

The double pulse mode combines the functions of the single pulse mode and the delayed pulse

mode. The primary p ulse oc curs imme diately a fter t he tr igger o ut and the secondar y pulse occurs

the programmed delay time after trigger out. The width of both pulses are equal t o t he p ulse

width clock range times the pulse width multiplier value. To pr event a pulse overrun, ensure that

the delay time and the pulse width do not extend into the next cycle. The pulse generation logic

takes about 75 nsec to start; therefore, ensure that the delay time + the pulse width is less than the

pulse repetition interval  75 nsec.