Jtag Emulator Pin Assignment Signal | CyClone COMPACTPCI-824

CPCI-824 User’s Manual Revision 1.0, January 2006

HARDWARE

Table 2-8. JTAG Emulator Pin Assignment

Signal	Pin	Pin	Signal

TDO	1	2	No Connect

TDI	3	4	TRST#

NO Connect	5	6	VREF

TCK	7	8	No Connect

TMS	9	10	No Connect

SYS_HALT#	11	12	No Connect

No Connect	11	12	No Connect

No Connect	15	16	GND

2-11

Image 21

CyClone COMPACTPCI-824 user manual Jtag Emulator Pin Assignment Signal

Contents

Page Chapter ContentsAppendix a Appendix B List of Tables List of Figures Contents Introduction CPCI-824 Block Diagram Sdram General Introduction Features General Introduction Specifications Environmental SpecificationsEnvironmental General Introduction CPCI-824 Physical Configuration Applied Micro Circuits Corporation Reference Manuals Software Development Amcc Powerpc 440GX Processor HardwareByte Ordering DDR Sdram Interface Hardware Memory MAP DDR DDR Sdram SdramInterrupts Interrupt External InterruptsInput Console Serial Port Console Serial Port Connector Pin Signal Description EthernetGigabit Ethernet Port Gigabit Ethernet Port LEDs 100 Fast Port Connector Pin Signal Description 10/100Base-TFast Ethernet Port Fast Ethernet Port LEDs Flash ROM Hardware Peripheral BUSLeds User LEDs During Initialization Breeze Start-up Leds LED TestsGeographic Addressing Power Supply Monitoring FAN Monitoring10 I2C BUS Jtag Emulator Support Sdram Eeprom Jtag Emulator Pin Assignment Signal Physical Attributes PMC Module Signal Definitions PMC Module Interface PMC Module ConnectorModule Idsel Addr IDSEL# Clock Arbitration ST Device ND Device Table A-3. P21 PMC Module Connector Pinout Table A-4. P22 PMC Module Connector Pinout Signal Table A-5. P23 PMC Module Connector Pinout Table B-1 CPCI-824 J2 Definition Appendix B Cpci J2 Definition