Cypress CY2291 manual Switching Waveforms, MHz/ms, Clock Jitter14 Peak-to-peak period jitter

								CY2291
Switching Characteristics, Industrial 3.3V (continued)
Parameter	Name		Description		Min.	Typ.	Max.		Unit
t6	Output Enable	Time for output to leave three-state mode after				10	15		ns
	Time	SHUTDOWN/OE goes HIGH
t7	Skew	Skew delay between any identical or related outputs[3,				< 0.25	0.5		ns
		12, 15]
t8	CPUCLK Slew	Frequency transition rate			1.0		20.0		MHz/ms
t9A	Clock Jitter[14]	Peak-to-peak period jitter (t9A Max. – t9A min.),% of				< 0.5	1		%
		clock period (fOUT < 4 MHz)
t9B	Clock Jitter[14]	Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz				< 0.7	1		ns
		< fOUT < 16 MHz)
t9C	Clock Jitter[14]	Peak-to-peak period jitter				< 400	500		ps
		(16 MHz < fOUT < 50 MHz)
t9D	Clock Jitter[14]	Peak-to-peak period jitter (fOUT > 50 MHz)				< 250	350		ps
t10A	Lock Time for	Lock Time from Power Up				< 25	50		ms
	CPLL
t10B	Lock Time for	Lock Time from Power Up				< 0.25	1		ms
	UPLL and SPLL
	Slew Limits	CPU PLL Slew Limits		CY2291I	8		66.6		MHz
				CY2291FI	8		60		MHz

Switching Waveforms

Figure 2. All Outputs, Duty Cycle and Rise/Fall Time

OUTPUT

t3

t1

t2

t4

OE

ALL THREE-STATE OUTPUTS

Figure 3. Output Three-State Timing [4]

t5

t6

CLK OUTPUT

RELATED CLK

Figure 4. CLK Outputs Jitter and Skew

t9A

t7

Document #: 38-07189 Rev. *C Page 9 of 12

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