CY2291
Document #: 38-07189 Rev. *C Page 6 of 12
VIH HIGH-Level Input Voltage[9] Except crystal pins 2.0 V
VIL LOW-Level Input Voltage[9] Except crystal pins 0.8 V
IIH Input HIGH Current VIN = VDD–0.5V < 1 10 μA
IIL Input LOW Current VIN = +0.5V < 1 10 μA
IOZ Output Leakage Current Three-state outputs 250 μA
IDD VDD Supply Current[10]
Industrial VDD = VDD max., 3.3V operation 50 70 mA
IDDS VDD Power Supply Current
in Shutdown Mode[10] Shutdown active,
excluding VBATT
CY2291I/CY2291FI 10 100 μA
IBATT VBATT Power Supply CurrentVBATT = 3.0V 5 15 μA
Switching Characteristics, Commercial 5.0V
Parameter Name Description Min. Typ. Max. Unit
t1Output Period Clock output range, 5V
operation CY2291 10
(100 MHz) 13000
(76.923 kHz) ns
CY2291F 11.1
(90 MHz) 13000
(76.923 kHz) ns
Output Duty
Cycle[11] Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT > 66 MHZ 40% 50% 60%
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT < 66 MHZ 45% 50% 55%
t3Rise Time Output clock rise time[13] 35ns
t4Fall Time Output clock fall time[13] 2.5 4 ns
t5Output Disable
Time Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW 10 15 ns
t6Output Enable
Time Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH 10 15 ns
t7Skew Skew delay between any identical or related outputs[3,
12, 15] < 0.25 0.5 ns
t8CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/m
s
t9A Clock Jitter[14] Peak-to-peak period jitter (t9A Max. – t9A min.),% of
clock period (fOUT < 4 MHz) < 0.5 1 %
t9B Clock Jitter[14] Peak-to-peak period jitter (t9B Max. – t9B min.)
(4 MHz < fOUT < 16 MHz) < 0.7 1 ns
t9C Clock Jitter[14] Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz) < 400 500 ps
t9D Clock Jitter[14] Peak-to-peak period jitter
(fOUT > 50 MHz) < 250 350 ps
t10A Lock Time for
CPLL Lock Time from Power Up < 25 50 ms
Electrical Characteristics, Industrial 3.3V (continued)
Parameter Description Conditions Min. Typ. Max. Unit
Notes
11.XBUF duty cycle depends on XTALIN duty cycle.
12.Measured at 1.4V.
13.Measured between 0.4V and 2.4V.
14.Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
note: “Jitter in PLL-Based Systems.”
15.CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
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