Preliminary Information
AMD Athlon™ XP Processor Model 10 Data Sheet | 26237C— May 2003 |
8.10General AC and DC Characteristics
Table 16 shows the AMD Athlon XP processor model 10 AC and DC characteristics of the Southbridge, JTAG, test, and miscel- laneous pins.
Table 16. General AC and DC Characteristics
Symbol | Parameter Description | Condition |
| Min |
| Max |
| Units |
| Notes | |
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VIH |
| Input High Voltage |
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| (VCC_CORE / 2) + |
| VCC_CORE | + | V |
| 1, 2 |
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| 200 mV |
| 300 mV |
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VIL |
| Input Low Voltage |
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| 350 |
| mV |
| 1, 2 | |
VOH |
| Output High Voltage |
|
| VCC_CORE – |
| VCC_CORE | + | mV |
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| 400 |
| 300 |
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VOL |
| Output Low Voltage |
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| 400 |
| mV |
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| |
ILEAK_P | Tristate Leakage Pullup | VIN = VSS |
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| mA |
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(Ground) |
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ILEAK_N | Tristate Leakage Pulldown | VIN = VCC_CORE |
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| 600 |
| ∝A |
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Nominal |
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IOH |
| Output High Current |
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| mA |
| 3 | |
IOL |
| Output Low Current |
|
| 6 |
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| mA |
| 3 |
TSU |
| Sync Input Setup Time |
|
| 2.0 |
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| ns |
| 4, 5 |
THD |
| Sync Input Hold Time |
|
| 0.0 |
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| ps |
| 4, 5 |
TDELAY | Output Delay with respect to RSTCLK |
|
| 0.0 |
| 6.1 |
| ns |
| 5 | |
Notes: |
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1. | Characterized across DC supply voltage range. |
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2. | Values specified at nominal VCC_CORE . Scale parameters between VCC_CORE. minimum and VCC_CORE. maximum. |
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3. | IOL and IOH are measured at VOL maximum and VOH minimum, respectively. |
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4. | Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. |
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5. | These are aggregate numbers. |
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6. | Edge rates indicate the range over which inputs were characterized. |
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7. | In asynchronous operation, the signal must persist for this time to enable capture. |
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8. | This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST. |
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9. | The approximate value for standard case in normal mode operation. |
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10. | This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency. |
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11. | Reassertions of the signal within this time are not guaranteed to be seen by the core. |
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12. | This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. |
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13. | This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other |
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14. | Time to valid is for any | in the | |||||||||
| information. |
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36 | Electrical Data | Chapter 8 |