Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C— May 2003

8.10General AC and DC Characteristics

Table 16 shows the AMD Athlon XP processor model 10 AC and DC characteristics of the Southbridge, JTAG, test, and miscel- laneous pins.

Table 16. General AC and DC Characteristics

Symbol

Parameter Description

Condition

 

Min

 

Max

 

Units

 

Notes

 

 

 

 

 

 

 

 

 

 

 

 

VIH

 

Input High Voltage

 

 

(VCC_CORE / 2) +

 

VCC_CORE

+

V

 

1, 2

 

 

 

200 mV

 

300 mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

 

Input Low Voltage

 

 

–300

 

350

 

mV

 

1, 2

VOH

 

Output High Voltage

 

 

VCC_CORE

 

VCC_CORE

+

mV

 

 

 

 

 

400

 

300

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL

 

Output Low Voltage

 

 

–300

 

400

 

mV

 

 

ILEAK_P

Tristate Leakage Pullup

VIN = VSS

 

–1

 

 

 

mA

 

 

(Ground)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILEAK_N

Tristate Leakage Pulldown

VIN = VCC_CORE

 

 

600

 

A

 

 

Nominal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOH

 

Output High Current

 

 

 

 

–6

 

mA

 

3

IOL

 

Output Low Current

 

 

6

 

 

 

mA

 

3

TSU

 

Sync Input Setup Time

 

 

2.0

 

 

 

ns

 

4, 5

THD

 

Sync Input Hold Time

 

 

0.0

 

 

 

ps

 

4, 5

TDELAY

Output Delay with respect to RSTCLK

 

 

0.0

 

6.1

 

ns

 

5

Notes:

 

 

 

 

 

 

 

 

 

 

 

1.

Characterized across DC supply voltage range.

 

 

 

 

 

 

 

 

 

2.

Values specified at nominal VCC_CORE . Scale parameters between VCC_CORE. minimum and VCC_CORE. maximum.

 

3.

IOL and IOH are measured at VOL maximum and VOH minimum, respectively.

 

 

 

 

 

4.

Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

 

 

 

 

 

5.

These are aggregate numbers.

 

 

 

 

 

 

 

 

 

6.

Edge rates indicate the range over which inputs were characterized.

 

 

 

 

 

 

 

 

7.

In asynchronous operation, the signal must persist for this time to enable capture.

 

 

 

 

 

8.

This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.

 

 

 

 

 

 

 

 

9.

The approximate value for standard case in normal mode operation.

 

 

 

 

 

10.

This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.

 

 

 

 

 

11.

Reassertions of the signal within this time are not guaranteed to be seen by the core.

 

 

 

 

 

12.

This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

 

 

 

 

13.

This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

 

 

configurations.

 

 

 

 

 

 

 

 

 

14.

Time to valid is for any open-drain pins. See requirements 7 and 8

in the “Power-Up Timing Requirements“ chapter for more

 

information.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

Electrical Data

Chapter 8

Page 48
Image 48
AMD 27493, 10, 27488 manual General AC and DC Characteristics