AMD 10, 27493, 27488 manual Processor Warm Reset Requirements, Clock Multiplier, Selection FID30

Models: 10 27493 27488

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Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C— May 2003

Clock Multiplier

The chipset samples the FID[3:0] signals in a chipset-specific

Selection (FID[3:0])

manner from the processor and uses this information to

 

determine the correct serial initialization packet (SIP). The

 

chipset then sends the SIP information to the processor for

 

configuration of the AMD Athlon system bus for the clock

 

multiplier that determines the processor frequency indicated

 

by the FID[3:0] code. The SIP is sent to the processor using the

 

SIP protocol. This protocol uses the PROCRDY, CONNECT, and

 

CLKFWDRST signals, that are synchronous to SYSCLK.

 

For more information about FID[3:0], see “FID[3:0] Pins” on

 

page 74.

 

Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and

 

AMD Duron™ System Bus Specification, order# 21902 for details

 

of the SIP protocol.

9.2Processor Warm Reset Requirements

Northbridge Reset RESET# cannot be asserted to the processor without also being

Pinsasserted to the Northbridge. RESET# to the Northbridge is the same as PCI RESET#. The minimum assertion for PCI RESET# is one millisecond. Southbridges enforce a minimum assertion of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0 milliseconds.

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Signal and Power-Up Requirements

Chapter 9

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AMD 10, 27493, 27488 manual Processor Warm Reset Requirements, Clock Multiplier, Selection FID30