Preliminary Information

26237C —May 2003

AMD Athlon™ XP Processor Model 10 Data Sheet

CLKIN, RSTCLK

Connect CLKIN with RSTCLK and name it SYSCLK. Connect

(SYSCLK) Pins

CLKIN# with RSTCLK# and name it SYSCLK#. Length match

 

the clocks from the clock generator to the Northbridge and

 

processor.

 

See “SYSCLK and SYSCLK#” on page 77 for more information.

CONNECT Pin

CONNECT is an input from the system used for power

 

management and clock-forward initialization at reset.

COREFB and

COREFB and COREFB# are outputs to the system that provide

COREFB# Pins

processor core voltage feedback to the system.

CPU_PRESENCE# Pin

CPU_PRESENCE# is connected to VSS on the processor

 

package. If pulled-up on the motherboard, CPU_PRESENCE#

 

may be used to detect the presence or absence of a processor in

 

the Socket A-style socket.

DBRDY and DBREQ#

DBRDY and DBREQ# are routed to the debug connector.

Pins

DBREQ# is tied to VCC_CORE with a pullup resistor.

FERR Pin

FERR is an output to the system that is asserted for any

 

unmasked numerical exception independent of the NE bit in

 

CR0. FERR is a push-pull active High signal that must be

 

inverted and level shifted to an active Low signal. For more

 

information about FERR and FERR#, see the “Required

 

Circuits” chapter of the AMD Athlon™ Processor-Based

 

Motherboard Design Guide, order# 24363.

Chapter 11

Pin Descriptions

73

Page 85
Image 85
AMD 10, 27493, 27488 manual Sysclk Pins, Connect Pin, Corefb, COREFB# Pins, Dbrdy and DBREQ#, Ferr Pin