Preliminary Information
AMD Athlon™ XP Processor Model 10 Data Sheet | 26237C— May 2003 |
| In C2, probes are allowed, as shown in Figure 3 on page 9 |
| The Stop Grant state is also entered for the S1, Powered On |
| Suspend, system sleep state based on a write to the SLP_TYP |
| and SLP_EN fields in the |
| control register in the Southbridge. During the S1 Sleep state, |
| system software ensures no bus master or probe activity occurs. |
| The Southbridge deasserts STPCLK# and brings the processor |
| out of the S1 Stop Grant state when any enabled resume event |
| occurs. |
Probe State | The Probe state is entered when the Northbridge connects the |
| AMD Athlon system bus to probe the processor (for example, to |
| snoop the processor caches) when the processor is in the Halt or |
| Stop Grant state. When in the Probe state, the processor |
| responds to a probe cycle in the same manner as when it is in |
| the Working state. When the probe has been serviced, the |
| processor returns to the same state as when it entered the |
| Probe state (Halt or Stop Grant state). When probe activity is |
| completed the processor only returns to a |
| the Northbridge disconnects the AMD Athlon system bus again. |
4.2 | Connect and Disconnect Protocol | |
|
| Significant power savings of the processor only occur if the |
|
| processor is disconnected from the system bus by the |
|
| Northbridge while in the Halt or Stop Grant state. The |
|
| Northbridge can optionally initiate a bus disconnect upon the |
|
| receipt of a Halt or Stop Grant special cycle. The option of |
|
| disconnecting is controlled by an enable bit in the Northbridge. |
|
| If the Northbridge requires the processor to service a probe |
|
| after the system bus has been disconnected, it must first |
|
| initiate a system bus connect. |
Connect Protocol | In addition to the legacy STPCLK# signal and the Halt and Stop | |
|
| Grant special cycles, the AMD Athlon system bus connect |
|
| protocol includes the CONNECT, PROCRDY, and CLKFWDRST |
|
| signals and a Connect special cycle. |
AMD Athlon system bus disconnects are initiated by the Northbridge in response to the receipt of a Halt or Stop Grant. Reconnect is initiated by the processor in response to an interrupt for Halt or STPCLK# deassertion. Reconnect is initiated by the Northbridge to probe the processor.
12 | Power Management | Chapter 4 |
